IC Package Design Engineer

What you'll do

• Perform physical layout of package substrates for SoC, Memory, RF, and cellular integrated circuits.
• Execute parasitic extraction and S-parameter modeling to validate Signal and Power Integrity performance targets.
• Own the physical design of packages, SiPs, and modules from initial concept through tape-out.
• Optimize package structure and configuration to meet system architecture and product design requirements.
• Develop automated design and verification flows using scripting languages like Python, Perl, or TCL.
• Evaluate new CAD tools and integrate AI technologies to improve design efficiency and quality.
• Ensure designs meet manufacturing constraints including DRC, DFM, and substrate fabrication rules.

What we're looking for

• Bachelor of Science degree.
• 10+ years of relevant industry experience.
• Experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms (preferred).
• Knowledge of diverse package types such as SiP, PoP, and wirebond (preferred).
• Expertise in high-speed interface layout constraints and Signal/Power Integrity analysis (preferred).
• Experience with simulation tools like HFSS or PowerSI and parasitic extraction (preferred).
• Knowledge of substrate manufacturing processes, design rules, and design for manufacturability (preferred).
• Proficiency in scripting languages such as Python, Perl, or TCL in a Unix/Linux environment (preferred).