IC Package Design Engineer

The IC Package Design Engineer joins the Packaging team to define, design, and integrate advanced electronic packaging solutions for internal and custom components across SoC, memory, RF, and cellular technologies. This role involves leading package architecture, optimizing structure configurations, and owning physical design from concept through tape-out. You will perform physical layout of substrates, execute parasitic extraction, and conduct S-parameter modeling to ensure Signal and Power Integrity performance targets are met. The work requires collaborating with cross-functional teams on system co-optimization while utilizing AI tools to enhance design efficiency. Key technical requirements include proficiency in Cadence Allegro or Mentor Xpedition, experience with Calibre and CAM350, and knowledge of high-speed interfaces like DDR and PCIe. Candidates should also possess skills in HFSS, PowerSI, and scripting languages such as Python, Perl, or TCL within Unix/Linux environments.