ASIC Physical Design Engineer

Cisco

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live today
Closes
Dec 1, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $189k
$141k $240k
below market most similar roles pay here above market

This role pays more than 51% of similar roles. Most pay $167,900–$218,000 — the blue band above. At the midpoint, this role pays about $189k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 284 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 210 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer

Role Posting Log in to save

The ASIC Physical Design Engineer joins the Silicon One team to support the development of hardware platforms for switching, routing, and wireless products. This role involves managing the full RTL-to-GDSII implementation flow for advanced semiconductor nodes, specifically focusing on 7nm, 5nm, and 3nm process technologies. Key responsibilities include hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks to optimize performance and die size. The engineer will analyze tool flows, guide clock tree synthesis strategies, and execute timing ECO implementations. Required technical skills include proficiency with EDA tools such as Innovus, Tempus, Primetime, Redhawk, Voltus, and Calibre, along with experience in Python, TCL, or Perl programming. The work addresses complex backend design challenges for high-performance networking chips.

Skills

RTL-to-GDSII Physical Design Static Timing Analysis STA Clock Tree Synthesis CTS Floorplanning Place and Route Power Integrity Equivalence Checks Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl DFT

What you'll do

  • Drive RTL-to-GDSII implementation including floorplanning, place and route, and static timing analysis.
  • Optimize design for performance, die size, power integrity, and equivalence checks.
  • Analyze existing tool flows to identify efficiency gaps and implement transformative enhancements.
  • Guide clock tree synthesis strategies and provide actionable feedback to implementation teams.
  • Execute STA setup, convergence methodologies, and sign-off processes across multi-mode and multi-corner scenarios.
  • Complete Timing ECO implementation using Tweaker and Primetime-based flows.
  • Evaluate various timing methodologies and tools across different technologies and design types.
  • Contribute to the automation of STA methodologies and design flow improvements.

What we're looking for

  • Bachelor’s Degree in Electrical Engineering with 5+ years of Physical Design experience.
  • Master’s Degree in Electrical Engineering with 3+ years of Physical Design experience.
  • PhD in Electrical Engineering with 0+ years of Physical Design experience.
  • Experience with RTL2GDSII flow and design tapeouts in 7nm, 5nm, 3nm, or below process technologies.
  • Experience with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre.
  • Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis (preferred).
  • Experience with static timing analysis, defining timing constraints, and corners/voltage definitions (preferred).
  • Experience with Python, TCL, or Perl programming (preferred).

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