GPU Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$195,200–$292,800 / yr
Posted
130 days ago
Freshness
Confirmed live yesterday
Closes
Oct 31, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $244k
$135k most similar roles pay here $310k

This role pays more than 81% of similar roles. Most pay $167,000–$235,750 — the shaded band above. At the midpoint, this role pays about $244k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · GPU Design Engineer

As a GPU Design Engineer, you will join the GPU ASICS Engineering team as a technical leader overseeing a high-performance RTL Design and Design Verification organization. You will manage a large team of engineers to drive architectural excellence, execution rigor, and product delivery for the Qualcomm family of GPU products. Your daily responsibilities include performing architecture reviews, defining micro-architecture, ensuring RTL quality, and managing verification strategies including constrained-random, coverage-driven verification, assertions, and formal techniques. You will navigate complex trade-offs regarding performance, power, area, and scalability while collaborating with cross-functional teams in physical design and software. The role requires deep expertise in SystemVerilog, Verilog, and ASIC design to solve technical challenges from micro-architecture through RTL freeze and verification sign-off for high-performance GPU, CPU, and ASIC designs.

What you'll do

  • Lead a high-performance RTL design and verification organization for the Qualcomm GPU product family.
  • Provide hands-on technical leadership in micro-architecture definition, RTL quality, and verification strategy.
  • Drive architectural trade-offs regarding performance, power, area (PPA), scalability, and product robustness.
  • Champion modern verification methodologies including constrained-random, coverage-driven verification, assertions, and formal techniques.
  • Manage a team of 11+ engineers by setting technical direction, hiring, and overseeing career development.
  • Oversee the full execution lifecycle from micro-architecture through RTL freeze and verification sign-off.
  • Identify and mitigate high-impact schedule or quality risks to ensure timely product delivery.
  • Establish and optimize processes and metrics to enable scale and sustained execution velocity.

What we're looking for

  • Must have a Bachelor's degree with 6+ years of experience, a Master's with 5+ years, or a PhD with 4+ years in a relevant engineering field.
  • Requires 20+ years of direct, relevant semiconductor industry experience in RTL design and/or design verification.
  • Must have proven experience managing large, high-performance engineering teams of at least 11 members.
  • Requires deep expertise in RTL design using SystemVerilog and Verilog.
  • Must have extensive experience delivering complex GPU, CPU, or ASIC designs from micro-architecture through silicon.
  • Must possess a strong understanding of micro-architecture, verification planning, coverage, debug, and tape-out readiness.
  • Must be able to provide hands-on technical leadership in RTL design, architecture reviews, and verification strategy.
  • Requires the ability to remain technically hands-on while operating at an executive and organizational leadership level.

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