below marketmost similar roles pay hereabove market
This role pays more than
85%
of similar roles. Most pay
$168,425–$235,750
— the blue band above.
At the midpoint, this role pays about
$255k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
JOB TITLE: GPU Design Engineer
The GPU ASICS Engineering team is seeking a Principal- or Director-level technical leader to head a high-performance RTL Design and Design Verification organization. This leader will manage a team of at least 11 engineers, providing hands-on technical guidance on micro-architecture definition, RTL quality, and verification strategy. Key responsibilities include driving architecture tradeoffs for performance, power, area, and scalability while overseeing execution from micro-architecture through RTL freeze and tape-out readiness. The role requires deep expertise in SystemVerilog, Verilog, and modern verification methodologies such as constrained-random, coverage-driven verification, assertions, and formal techniques. The position focuses on delivering complex GPU, CPU, and ASIC designs, ensuring rigorous sign-off discipline and technical excellence across the Qualcomm family of GPU products to resolve high-impact schedule and quality risks.
Lead a high-performance RTL design and design verification organization for Qualcomm GPU development.
Provide hands-on technical leadership for architecture reviews, micro-architecture definition, and RTL quality.
Drive best-in-class RTL quality, verification coverage, and sign-off discipline across GPU products.
Influence architecture tradeoffs related to performance, power, area, scalability, and product robustness.
Champion modern verification methodologies including constrained-random, coverage-driven verification, and formal techniques.
Build and scale an engineering organization of 11+ engineers including hiring and succession planning.
Manage program execution from micro-architecture through RTL freeze and verification sign-off.
Identify and mitigate technical risks to ensure predictable delivery of complex ASIC designs.
What we're looking for
Possess a Master's Degree in Computer Science or Electrical Engineering and 20+ years of direct, relevant semiconductor industry experience in RTL design and/or design verification.
Possess a Bachelor's degree in a related field and 6+ years of engineering experience, or a PhD and 4+ years of engineering experience.
Proven track record of building, leading, and scaling a high-performance organization of at least 11+ RTL and DV engineers.
Deep expertise in RTL design using SystemVerilog/Verilog and design verification methodologies.
Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture through silicon.
Strong understanding of micro-architecture, verification planning, coverage, debug, and tape-out readiness.
Ability to remain technically hands-on while operating effectively at the executive and organizational leadership level.
Proven program and execution excellence with the ability to drive predictable and disciplined execution.
ASIC Implementation
Physical Design
Place and Route
PPA Optimization
Synthesis
DFT
Floorplanning
TCL
Perl
Python
RTL
Power Distribution
Physical Signoff
Design for Yield
Thermal Management
multi Vt
ASIC Implementation
Physical Design
Place and Route
Synthesis
DFT
Floorplanning
PPA Optimization
TCL
Perl
Python
RTL
Clock and Power Distribution
Physical Signoff
Design for Yield
Thermal Management
multi Vt
Physical Design
ASIC Implementation
Place and Route
Floorplanning
Synthesis
DFT
Clock and Power Distribution
RTL
Multi-voltage
Power Retention
Design for Yield
Manufacturability
Thermal Management
Tapeout