FE Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $200k

$125k most similar roles pay here $236k

This role pays more than 69% of similar roles. Most pay $139,875–$214,000 — the shaded band above. At the midpoint, this role pays about $200k versus about $177k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineer

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FE Engineer will join the hardware team to focus on front-end design synthesis and large chip integration. The role involves performing timing analysis, formal verification, lint checks, and designing multi-clock and multi-power-domain systems. Day-to-day responsibilities include managing floor-planning, placement, congestion, and setup/hold timing closure while working on ECOs for functionality and timing. The engineer will propose RTL transforms to reduce power and area, script and program with DFT insertion, and perform PPA optimization of the netlist. Key technical requirements include proficiency in System Verilog or VHDL, logic synthesis using Synopsys Design Compiler or Cadence Genus, and scripting in TCL, Perl, or Python. The work involves solving complex hardware problems related to CPUs, GPUs, or DSPs while ensuring netlist quality through Lint, CDC, and logic equivalence checks.

Skills

System Verilog VHDL Verilog RTL TCL Python Perl Linux Unix Synopsys Design Compiler Cadence Genus DFT CDC Lint Logic Synthesis Timing Analysis PPA Optimization Netlist Generation

What you'll do

Perform front-end design synthesis and large chip integration.
Conduct timing analysis, formal verification, and lint checks.
Design multi-clock and multi-power-domain systems.
Execute floor-planning, placement, and setup/hold timing closure.
Propose RTL transforms to reduce power and area.
Script and program for DFT insertion using TCL, Perl, or Python.
Perform PPA optimization of the netlist.
Deliver key netlist quality milestones including CDC and logic equivalence checks.

What we're looking for

Bachelor's degree or foreign equivalent in Robotics Engineering, Electrical Engineering, Electronics Engineering, or a related field.
Experience using hardware description coding languages (RTL) such as System Verilog, Verilog, or VHDL.
Experience with logic synthesis using tools like Synopsys Design Compiler or Cadence Genus.
Proficiency in Unix or Linux environments and scripting capabilities in TCL, Perl, or Python.
Experience performing statistical timing analysis in industry tools.
Ability to analyze timing and area reports and implement improvements.
Experience using industry standard tools for Lint structural checking, clock CDC, or reset domain crossing RDC analysis.
Experience using logic equivalence flow tools to check synthesis results for correct RTL to gate translation.

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