FE Engineering

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $181k

This role $200k

$121k most similar roles pay here $236k

This role pays more than 68% of similar roles. Most pay $142,575–$219,131 — the shaded band above. At the midpoint, this role pays about $200k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineering

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The FE Engineering role involves designing pre-silicon hardware emulation and prototyping platforms for wireless ICs. The engineer will be responsible for understanding system requirements, designing Verilog RTL for signal processing blocks, and developing firmware or software in C, C++, or SystemC to control hardware blocks. Day-to-day tasks include working with SoC design and verification teams to deliver designs to emulation and prototyping teams, as well as triaging design and performance issues during platform bring-up. The role requires proficiency in SystemC, high-level synthesis methodology, MATLAB for modeling signal processing blocks, and the use of FPGA and emulation platforms like HAPS, Palladium, and Protium. Additionally, the candidate must utilize synthesis and timing closure tools to evaluate area, timing, and power while performing quality checks for CDC and DFT.

Skills

SystemC Verilog SystemVerilog VHDL RTL FPGA HAPS Palladium Protium C C++ MATLAB High-Level Synthesis SoC Design Design Verification CDC DFT Timing Closure

What you'll do

Design pre-silicon hardware emulation and prototyping platforms using SystemC and high-level synthesis methodology.
Design Verilog RTL for signal processing blocks in wireless integrated circuits.
Develop firmware or software in C, C++, or SystemC to control hardware blocks.
Model and simulate signal processing blocks using MATLAB.
Utilize FPGA and emulation platforms like HAPS, Palladium, and Protium for testing and bring-up.
Debug design and performance issues during platform bring-up in coordination with silicon validation and software teams.
Evaluate area, timing, and power of RTL blocks using synthesis and timing closure tools.
Perform quality checks for Clock Domain Crossing (CDC) and Design for Test (DFT).

What we're looking for

Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
At least 1 year of experience in the job offered or a related occupation.
Experience using SystemVerilog, Verilog, or VHDL to design RTL for signal processing blocks.
Experience writing firmware or software in C, C++, or SystemC to control hardware blocks.
Experience using MATLAB for modeling and simulating signal processing blocks.
Experience using FPGA and emulation platforms for the test and bring-up of RTL blocks.
Experience debugging issues found on FPGA and emulation platforms.
Experience utilizing synthesis and timing closure tools to evaluate area, timing, and power of RTL blocks.

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