FE Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $200k

$125k most similar roles pay here $236k

This role pays more than 69% of similar roles. Most pay $139,875–$214,000 — the shaded band above. At the midpoint, this role pays about $200k versus about $177k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · FE Engineer

Role Posting Log in to save

FE Engineer The FE Engineer joins the SoC Design, Soc Design Verification, System Verification, STA, and Physical Design teams to implement designs and flows for sophisticated SoCs. This role involves developing micro-architecture and design specifications, implementing and verifying complex logic designs, and optimizing power and performance. The engineer will integrate various IPs while ensuring designs meet DFT, CDC, Synthesis, Static Timing, and Power Requirements. Day-to-day tasks include collaborating with CAD and Flow teams to improve front-end methodologies and writing technical documentation. Key technologies and skills include System Verilog or Verilog for wireless communication IPs, scripting languages like Python, Perl, or TCL for automation, and tools from Synopsys and Cadence. The role addresses critical hardware challenges including clock/power gating, high-speed interface design, and low power methodologies such as UPF/CPF to ensure robust digital logic functionality across multiple domains.

Skills

System Verilog Verilog RTL Python Perl TCL CDC RDC UPF CPF Synopsys Cadence LEC LEQ SoC DVFS Synthesis

What you'll do

Develop RTL designs for one or more blocks based on microarchitecture specifications and design guidelines.
Implement and verify sophisticated logic designs while optimizing for power and performance.
Integrate various IPs ensuring the design meets DFT, CDC, Synthesis/Static Timing, and Power requirements.
Develop micro-architecture and design specifications for complex SoC components.
Automate RTL integration flows, synthesis, and timing reports using scripting languages like Python, Perl, or TCL.
Implement low power methodologies including UPF/CPF, clock gating, power gating, and DVFS.
Resolve issues related to multiple clock domains and reset domains using CDC and RDC tools.
Define and improve front-end design methodologies in collaboration with CAD and Flow teams.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
Experience writing RTL for wireless communication IPs using System Verilog or Verilog.
Proficiency in scripting languages such as Python, Perl, or TCL for automation and building hardware modules.
Knowledge of CDC and RDC tools to manage multiple clock and reset domains.
Experience with RTL design involving complex FSMs and power-saving features.
Experience in IP integration including clock/reset module design and fabric/bus-system configuration.
Ability to implement low-power methodologies such as UPF, CPF, and various check techniques.
Proficiency with Synopsys or Cadence synthesis tools, LEC/LEQ tools, and ECOs.

Similar roles

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $150,400–$225,300

System Verilog Verilog RTL Python Perl TCL Cadence Synopsys Computer Architecture Digital Logic Design Assertion Methodology Power Closure Synthesis Physical Verification Signal Integrity Cache Coherence

Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300

System Verilog VHDL Verilog RTL TCL Python Perl Linux Unix Synopsys Design Compiler Cadence Genus DFT CDC Lint Logic Synthesis Timing Analysis PPA Optimization Netlist Generation

Save

FE Engineer

Apple Inc

Austin, TX 16 days ago

System Verilog Verilog RTL Synthesis Timing Closure Cadence Synopsys DFT Low Power Design Clock Gating Power Gating DVFS Netlist Generation SOC CAD Tools

Save

FE Engineer

Apple Inc

Cupertino, CA 16 days ago $150,400–$225,300

System Verilog Verilog RTL Design SoC CDC AMBA AHB STA Lint Tools Simulation Tools Analog IP Front-end Synthesis

2+ yrs exp

Save

Front End Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300

Python Pandas Matplotlib Seaborn scikit-learn Tableau Splunk VLSI Digital Logic System Software Memory-mapped I/O

Save

FE Engineer

Apple Inc

Austin, TX 2 days ago

Verilog RTL Design Cache Coherency Protocols Verdi Micro-architecture Gate-level Design LEC LEQ Clock Gating Power Gating Bus Gating Simulation Testbench Development

Save