FE Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $177k

This role $188k

$125k most similar roles pay here $236k

This role pays more than 59% of similar roles. Most pay $139,875–$214,000 — the shaded band above. At the midpoint, this role pays about $188k versus about $177k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineer

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FE Engineer The FE Engineer joins the hardware team to design and develop hardware for mobile devices, specifically focusing on Central Processing Unit (CPU) hardware. The role involves evaluating new features, defining micro-architecture, and developing CPU hardware using a Hardware-Description-Language. Key responsibilities include performing functional debug, achieving timing and power closure for target specifications, and preparing design documentation. Candidates will work with System Verilog or Verilog to write RTL for high-speed communication IPs and manage complex FSMs and power saving features. The role requires proficiency in scripting languages like Python, Perl, or TCL to automate integration flows and build hardware models. Technical expertise must include computer architecture, logic design of standard interfaces, cache coherence, and physical verification using Cadence or Synopsys tools while addressing device physics issues like leakage power and signal integrity.

Skills

System Verilog Verilog RTL Python Perl TCL Cadence Synopsys Computer Architecture Digital Logic Design Assertion Methodology Power Closure Synthesis Physical Verification Signal Integrity Cache Coherence

What you'll do

Design and develop hardware for Apple's mobile devices.
Evaluate new ideas and features for Central Processing Unit (CPU) hardware.
Define the micro-architecture of CPU hardware.
Develop CPU hardware using Hardware Description Languages like SystemVerilog or Verilog.
Perform functional debug, timing closure, and power closure for target specifications.
Automate RTL integration flows, verification processes, and reporting using Python, Perl, or TCL.
Manage complex data path logic to meet performance, area, and power goals.
Prepare technical documentation of the Design Specification.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience using System Verilog or Verilog to write RTL for high-speed communication IPs.
Experience in RTL design utilizing System Verilog or Verilog with complex FSMs and power saving features.
Proficiency in scripting languages like Python, Perl, or TCL for automation and building hardware models.
Experience in computer architecture and logic design of industry standard interfaces.
Knowledge of digital logic design principles including cache coherence and hardware-software interactions.
Familiarity with constrained random verification, functional coverage, code coverage, and assertion methodology.
Experience with physical design tools from Cadence or Synopsys for placement, clock tree synthesis, routing, or physical verification.

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