FE Engineering

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $148,987–$194,700 / yr
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k

This role $172k

$124k most similar roles pay here $229k

This role pays less than 53% of similar roles. Most pay $142,575–$219,131 — the shaded band above. At the midpoint, this role pays about $172k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineering

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FE Engineering works on the timing closure aspect of ASIC chips using deep sub-micron processes for high-end mobile applications. The role involves managing SoC design efforts, developing and enhancing timing constraints for complex multi-clock and multi-voltage systems, and creating coverage analysis scripts for critical path analysis and hard macro interfaces. Responsibilities include owning full chip and block level timing closure throughout the project cycle from RTL through physical implementation, while maintaining methodologies for timing verification. The position requires expertise in digital and analog electronic circuits to address issues like voltage drops, temperature effects, and signal integrity. Candidates must be proficient in Register Transfer Level programming languages such as Verilog or VHDL, along with C/C++ or Python for automating report parsing and refining constraints within the Static Timing Analysis modeling framework.

Skills

STA SoC Verilog VHDL Python C++ RTL ASIC Timing Closure Synthesis Physical Implementation Finite State Machine Signal Integrity

What you'll do

Achieve timing closure for ASIC chips using deep sub-micron processes.
Develop and enhance timing constraints for complex, multi-clock, and multi-voltage SoCs.
Create scripts for critical path analysis, coverage checks, and hard macro interfaces.
Manage full chip and block level timing ownership through RTL, synthesis, and physical implementation.
Resolve complex timing issues for major building blocks of high-end mobile SoC chips.
Develop and maintain methodologies and flows related to timing verification and closure.
Analyze setup/hold violations and interpret timing relationships in digital electronic circuits.
Automate report parsing and slack distribution analysis using Python or C++.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience or education in digital electronic circuits including combinational and sequential logic gates to identify critical timing paths and analyze violations.
Understanding of analog electronic circuits and how factors like voltage, temperature, and signal integrity affect chip timing.
Knowledge of computer systems and architecture to model SoC interconnections through awareness of pipeline structure and memory hierarchy.
Ability to use finite state machine design to define correct design constraints such as multi-cycle paths or false path exceptions.
Proficiency in RTL programming languages like Verilog or VHDL to debug synthesized netlists and timing violations.
Proficiency in programming languages like C/C++ or Python for automating report parsing and analyzing slack distributions.

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