FE Engineering

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$225,300 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $188k
$123k most similar roles pay here $236k

This role pays more than 60% of similar roles. Most pay $142,575–$219,131 — the shaded band above. At the midpoint, this role pays about $188k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · FE Engineering

Role Posting Log in to save

FE Engineering involves developing complex digital IPs for Power Management ICs (PMICs) while meeting specific schedule, area, power, and performance targets. The role focuses on performing RTL design in SystemVerilog for digital control logic, including the implementation of FSMs and other control structures. You will collaborate with cross-functional teams to develop precise design specifications and synthesize RTL designs into gates using Synopsys Design Compiler or Cadence Genus. Key responsibilities include analyzing PPA impact via PrimeTime PX, implementing low-power techniques like clock and power gating, and performing CDC and RDC analysis. You will also conduct functional verification using Cadence Xcelium and Simvision while utilizing Perl and Python for ASIC flow development. This role addresses the technical challenge of ensuring reliable data transfer and robust logic in multi-clock designs to meet critical silicon tapeout requirements.

Skills

SystemVerilog RTL Design ASIC Synopsys Design Compiler Cadence Genus PrimeTime PX Cadence Xcelium SimVision Python Perl CDC RDC SDC gate level netlist Power Management ICs

What you'll do

  • Design complex digital IPs and control logic using SystemVerilog for Power Management ICs (PMICs).
  • Synthesize RTL designs into gates while analyzing Power, Performance, and Area (PPA) impacts using industry-standard tools.
  • Implement low-power design techniques including clock and power gating to meet specific targets.
  • Perform RTL simulation and functional verification using Cadence Xcelium or Simvision to ensure correct functionality.
  • Conduct Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and verification.
  • Manage design signoff duties, including the cleanup of SDC, CDC, and other constraint files.
  • Develop ASIC flow tasks and automation scripts using Perl and Python.
  • Support Silicon Validation by explaining design functionality and providing debugging assistance for test plans.

What we're looking for

  • Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
  • Experience designing digital logic in ASIC using SystemVerilog to implement specific functionalities and features.
  • Experience simulating ASIC designs using Cadence or Synopsys SystemVerilog Simulators to verify functional correctness.
  • Experience analyzing circuit behavior in Cadence Indago or SimVision to debug design issues and trace signal propagation.
  • Experience synthesizing design into ASIC library gates using Synopsys Design Compiler or Cadence Genus for PPA optimization.
  • Experience using CDC tools to verify clock domain crossings and RDC tools to verify reset domain crossings.
  • Experience performing chip tapeout signoff duties, including reviewing constraint files and STA reports.
  • Experience generating power reports and using Synopsys PrimeTime for RTL and gate-level power estimation.

Related searches

More FE Engineering jobs FE Engineering jobs in Cupertino All jobs at Apple Inc

More like this

Similar roles

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $150,400–$225,300
System Verilog Verilog RTL Python Perl TCL Cadence Synopsys Computer Architecture Digital Logic Design Assertion Methodology Power Closure Synthesis Physical Verification Signal Integrity Cache Coherence
Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300
System Verilog VHDL Verilog RTL TCL Python Perl Linux Unix Synopsys Design Compiler Cadence Genus DFT CDC Lint Logic Synthesis Timing Analysis PPA Optimization Netlist Generation
Save

FE Engineering

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300
SystemC Verilog SystemVerilog VHDL RTL FPGA HAPS Palladium Protium C C++ MATLAB High-Level Synthesis SoC Design Design Verification CDC DFT Timing Closure
1+ yrs exp
Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300
System Verilog Verilog RTL Python Perl TCL CDC RDC UPF CPF Synopsys Cadence LEC LEQ SoC DVFS Synthesis
Save

FE Engineer

Apple Inc

Cupertino, CA 16 days ago $150,400–$225,300
System Verilog Verilog RTL Design SoC CDC AMBA AHB STA Lint Tools Simulation Tools Analog IP Front-end Synthesis
2+ yrs exp
Save

FE Engineer

Apple Inc

Austin, TX 2 days ago
Verilog System Verilog RTL SoC AHB AXI ARM RISCV Python C++ Perl Perforce GitHub STA Netlist
2+ yrs exp
Save