This role pays more than
59%
of similar roles. Most pay
$139,000–$214,562
— the shaded band above.
At the midpoint, this role pays about
$188k
versus about
$177k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3587 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2768 roles with salary data.
As an FE Engineer, you will work with leads and architecture teams to define design microarchitecture and develop RTL designs for one or more blocks following established guidelines. You will own all aspects of RTL development, integrate common or shared IP blocks, and optimize memories and hard macros required for the block. Your daily responsibilities include performing front-end synthesis and STA to ensure timing is met while optimizing power and performance. To succeed in this role, you must utilize SystemVerilog or Verilog for CPU-based SoCs, apply CDC tools for multiple clock domains, and work with AMBA protocols like AHB. You will also use industry standard simulation tools, LINT tools, and debug system silicon functionality during chip bring-up while managing digital and analog IP integrations at the SoC level.
Define design microarchitecture in coordination with leads and architecture teams.
Develop RTL designs for specific blocks based on established microarchitecture specifications.
Integrate common/shared IP blocks and optimize memories and hard macros.
Perform front-end synthesis and Static Timing Analysis (STA) to ensure timing goals are met.
Optimize power and performance metrics for the assigned hardware blocks.
Implement CDC tools and techniques to manage multiple clock domains.
Verify and debug functional behavior of SoC or IP block-level designs using industry standard simulation tools.
Validate and debug system silicon functionality during the chip bring-up phase.
What we're looking for
Master's degree or foreign equivalent in Electrical Engineering or a related field.
2 years of experience in the job offered or a related occupation.
2 years of experience using System Verilog or Verilog to write RTL for CPU-based SoCs.
2 years of experience utilizing CDC tools and techniques with knowledge of multiple clock domains.
2 years of experience in RTL Design with AMBA protocols, such as AHB.
2 years of experience using industry standard simulation tools to verify and debug SoC or IP block designs.
2 years of experience configuring and integrating digital and analog IPs into an SoC/sub-system.
2 years of experience analyzing timing and resolving violations at digital-analog interfaces, utilizing LINT tools, and debugging silicon during chip bring-up.