FE Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $172k

$121k $225k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $130,744–$214,000.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · FE Engineer

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As an FE Engineer, you will join a dynamic group to design, integrate, and verify a system fabric bus into a subsystem. Your primary responsibilities include building a test bench, creating test vectors, and running verification environments to ensure the subsystem functions correctly. You will also synthesize the subsystem into logic and perform Static Timing Analysis to meet specific timing requirements while prioritizing flexibility and reusability in the platform design. The role requires proficiency in Verilog and System Verilog RTL language design entry, along with experience using Synopsys and Cadence synthesis tools. You must be skilled in Synopsys PrimeTime Static Timing Analysis and Synopsys VCS or Cadence Incisive simulation. This position focuses on the technical challenge of front-end design integration for hardware products.

Skills

System Verilog Verilog RTL Static Timing Analysis STA Synopsys Cadence VCS Incisive PrimeTime Digital Logic Design Synthesis Verification Test Bench Logic Design

What you'll do

Design, integrate, and verify a system fabric bus into a subsystem.
Build the platform with a focus on flexibility and reusability.
Build test benches and create test vectors to verify subsystem functionality.
Run verification environments to ensure the designed subsystem works properly.
Synthesize the subsystem into logic using Synopsys or Cadence tools.
Perform Static Timing Analysis (STA) to ensure the design meets timing requirements.
Write technical specifications and documentation for the hardware design.

What we're looking for

Knowledge of digital logic design.
Proficiency in Verilog and System Verilog RTL language design entry.
Experience with Synopsys or Cadence synthesis tools.
Proficiency in Synopsys PrimeTime Static Timing Analysis (STA).
Experience with Synopsys (VCS) or Cadence (Incisive) simulation.
Strong problem-solving and analytical skills.
Strong communication skills and a team-oriented approach to verification efforts.
Experience writing specifications and documentation (preferred).

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