DFT Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $153,600–$215,000 / yr
Posted: 59 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $170k

This role $184k

$135k $224k

below market most similar roles pay here above market

This role pays more than 80% of similar roles. Most pay $155,450–$184,300 — the blue band above. At the midpoint, this role pays about $184k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · DFT Engineer

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DFT Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. The role involves architecting and defining DFT solutions for various chips, contributing to IP and methodology improvements using AI flows, and incorporating DFT logic like MBIST, clock controls, and JTAG controllers. You will collaborate with ASIC design teams, RFIC teams to ensure fault coverage on custom RF blocks, and test engineering teams to translate ATE patterns and perform joint bring-ups. Required skills include experience in advanced DFT techniques for deep sub-micron nodes, developing automated scripts for DFT insertion and validation, and knowledge of Logic BIST. The work focuses on modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

Skills

DFT MBIST JTAG ASIC Design RFIC Mixed Signal ATE AI/ML CMOS

What you'll do

Architect and define DFT solutions tailored to the specific requirements of various LEO chips.
Improve and customize IPs and DFT methodologies while integrating AI-based flows.
Incorporate MBIST, clock controls, and JTAG controllers into the ASIC design.
Collaborate with RFIC teams to achieve maximum fault coverage on custom RF blocks.
Ensure blocks meet specific DFT, timing, and power targets during implementation.
Translate ATE patterns into tester formats in coordination with the Test engineering team.
Jointly perform the bring-up of the digital portions of the LEO chips.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
2+ years of experience in advanced DFT techniques for deep sub-micron nodes.
Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.
Master's degree in Electrical or Communications Engineering or a related field (preferred).
5+ years of experience in DFT, including exposure to Loggic BIST (preferred).
Familiarity working with RFIC engineers on chips that have a large Mixed signal component (preferred).
Experience with automotive standards and ways to achieve single digit DPPM targets (preferred).
Export control laws and regulations, candidates.