Senior DFT Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $159,200–$215,300 / yr
Posted: 13 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $174k

This role $187k

$135k most similar roles pay here $224k

This role pays more than 81% of similar roles. Most pay $160,000–$187,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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Sr. DFT Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and gateways. This role involves architecting and defining DFT solutions tailored to specific LEO chips while improving and customizing IPs and DFT methodology using AI flows. The engineer will collaborate with ASIC design teams to incorporate MBIST, clock controls, and JTAG controllers, and work with RFIC teams to ensure maximum fault coverage on custom RF blocks. Key responsibilities include ensuring blocks meet timing and power targets, translating ATE patterns to tester formats, and performing joint bring-ups of digital portions. Required expertise includes advanced DFT techniques for deep sub-micron nodes, automated script development for insertion and validation, and experience with mixed-signal components in the latest CMOS generation technologies.

Skills

DFT MBIST JTAG ASIC RFIC Mixed signal CMOS AI/ML ATE Automotive Standards

What you'll do

Architect and define DFT solutions tailored to the specific requirements of LEO chips.
Improve and customize IPs and DFT methodologies while integrating AI-driven workflows.
Integrate DFT logic such as MBIST, clock controls, and JTAG controllers into ASIC designs.
Collaborate with RFIC teams to ensure maximum fault coverage for custom RF blocks.
Ensure all blocks meet specific DFT, timing, and power targets during implementation.
Translate ATE patterns into tester formats in coordination with the test engineering team.
Perform joint bring-up of the digital portions of LEO chips with the test team.

What we're looking for

Bachelor's degree in Electrical/Communications Engineering or equivalent experience in the electrical engineering field.
5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.
Master's or Ph.D. degree in Electrical/Communications Engineering is preferred.
7+ years of experience in DFT, including exposure to Logic BIST, is preferred.
Familiarity working with RFIC engineers on chips with large mixed-signal components.
Must be a U.S. citizen, national, permanent resident, or lawfully admitted as a refugee or granted asylum.
Export control laws and regulations, candidates.