Senior DFT Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $185,200–$250,000 / yr
Posted: 59 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $174k

This role $218k

$131k $263k

below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $160,000–$187,250 — the blue band above. At the midpoint, this role pays about $218k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer

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The Sr. DFT Engineer joins the Amazon Leo sub-team to define and implement digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This role involves architecting and defining DFT solutions for various chips, contributing to the customization of IPs and DFT methodology while embracing AI flow. Day-to-day responsibilities include incorporating MBIST, clock controls, and JTAG controllers into ASIC designs, ensuring maximum fault coverage on custom RF blocks, and meeting timing and power targets. The engineer will also translate ATE patterns to tester formats and jointly bring up digital portions of the chips. Required skills include advanced DFT techniques for deep sub-micron nodes, automated script development for insertion and validation, and experience with mixed-signal components and automotive standards.

Skills

DFT MBIST JTAG ASIC Design RFIC Mixed Signal ATE AI/ML CMOS Hardware Development

What you'll do

Architect and define DFT solutions tailored to specific LEO chip requirements.
Customize IPs and DFT methodologies while integrating AI-based flows.
Incorporate MBIST, clock controls, and JTAG controllers into ASIC designs.
Collaborate with RFIC teams to achieve maximum fault coverage on custom RF blocks.
Ensure blocks meet DFT, timing, and power targets during implementation.
Translate ATE patterns to tester formats for the test engineering team.
Jointly perform bring-up of the digital portions of the LEO chips.

What we're looking for

Bachelor's degree in Electrical/Communications Engineering, or experience working in the electrical engineering field.
5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.
Must be a U.S. citizen, national, permanent resident, refugee, or granted asylum.
Master's or Ph.D. degree in Electrical / Communications Engineering (preferred).
7+ years of experience in DFT, including exposure to Logic BIST (preferred).
Familiarity working with RFIC engineers on chips with a large Mixed signal component (preferred).
Export control laws and regulations, candidates.

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