Design Verification Lead

What you'll do

• Lead, grow, and mentor a team of verification engineers through technical guidance and performance management.
• Define and implement scalable, reusable, and efficient verification strategies for silicon IPs.
• Develop functional and power-aware verification plans using SystemVerilog and UVM methodologies.
• Drive verification requirements, planning, and environment implementation in collaboration with architecture and design teams.
• Execute test coverage, formal verification, and assertion-based verification to ensure first-pass silicon success.
• Review team members' work and provide technical leadership to foster a culture of innovation.
• Refine verification strategies continuously to improve efficiency, speed, and completeness.

What we're looking for

• Minimum of 20 years relevant industry experience.
• 12+ years of experience in ASIC/SoC verification, including at least 3 years in a senior leadership role managing teams of engineers (preferred).
• Deep expertise in SystemVerilog, UVM, and modern verification methodologies (preferred).
• Experience with post-silicon validation and debug (preferred).
• Hands-on experience with low-power design verification, including UPF methodology and power intent validation (preferred).
• Background in high-speed interfaces, formal verification, and constrained-random testbenches (preferred).
• Experience leading multi-site teams and cross-functional collaboration with architecture, design, and software groups (preferred).