Design Verification Lead

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$175,500–$311,700 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $244k
$128k $331k
below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$233,050 — the blue band above. At the midpoint, this role pays about $244k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Design Verification Lead

The Design Verification Lead joins the Custom Silicon Management Group to lead the design verification front for vendor silicons, including power, display, touch, sensors, and accessories. This role involves managing the entire project phase from specification and planning to execution and final sign-off. You will work with multi-functional internal teams and external vendors to review specifications, improve verification plans, and ensure full coverage for next-generation mobile solutions. Key responsibilities include tracking progress, reviewing architecture, and providing technical guidance on long-term technology roadmaps. The role requires expertise in SystemVerilog and UVM, along with knowledge of ASIC architecture, constrained random verification, functional coverage, assertions, and GLS. Additional experience with Formal verification, low power verification, and analog mixed signal simulation is also preferred.

What you'll do

  • Lead the design verification front for vendor silicons including power, display, touch, and sensors.
  • Manage the entire project lifecycle from initial specification and planning to execution and final sign-off.
  • Review specifications and improve verification plans and methodologies to ensure full coverage.
  • Collaborate with design and micro-architecture teams to define functional and performance goals.
  • Track design verification progress, quality, architecture, and implementation metrics.
  • Provide technical guidance for planning, execution, and long-term technology roadmaps.
  • Drive technical engagements between internal teams and external silicon suppliers.

What we're looking for

  • BS degree and 10 years of industry experience.
  • Experience with modern verification languages, including SystemVerilog / UVM.
  • Advanced knowledge of ASIC architecture, design, and verification flow (preferred).
  • Expert knowledge of state-of-the-art verification flow and methodology, such as constrained random, functional/code coverage, assertions, and GLS (preferred).
  • Knowledge of Formal verification, low power verification, and analog mixed signal simulation (preferred).
  • Knowledge of industry standard interfaces (preferred).
  • Excellent social and communication skills, team spirit, and the passion to take on diverse challenges (preferred).

More like this

Similar roles

Design Verification Lead

Apple Inc

Austin, TX 40 days ago
SystemVerilog UVM ASIC SoC Formal Verification UPF Power-Aware Verification Coverage-Driven Verification Post-Silicon Validation PCIe USB DDR Emulation Prototyping
10+ yrs exp

Design Verification Engineer

Apple Inc

San Diego, CA 40 days ago $175,000–$308,500
SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Data Structures and Algorithms
10+ yrs exp

Design Verification Engineer

Apple Inc

Waltham, MA 59 days ago $165,800–$292,400
SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP
10+ yrs exp

Design Verification Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Data Structures and Algorithms
3+ yrs exp

Lead Design Verification Engineer, Memory Controller

Amd

San Jose, CA 35 days ago $200,000–$300,000
System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management
8+ yrs exp

Design Verification Technical Leader

Cisco

Carlsbad, CA +1 5 days ago $192,400–$275,800
System Verilog UVM ASIC Design Verification Python Perl TCL Shell Scripts Verilog Formal Verification Veloce HAPS Ethernet UCIE UAL SPI I2C SerDes D2D PHY ODSP
8+ yrs exp Hybrid