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As a Design Verification Engineer, you will join the team to ensure the RTL design of the GPU is functionally correct and bug-free. Your daily responsibilities involve running numerous tests, analyzing waveforms and logs to debug failures, and collaborating with designers to revise tests for corner cases. You will also be responsible for creating verification plans based on architectural specifications, collecting test data to ensure full design coverage, and developing scripts to automate verification flows. The role requires proficiency in SystemVerilog and experience with modern modeling, simulation, and synthesis tools. You must possess expertise in register-transfer and logic levels of complex digital systems, including knowledge of machine-level code, memory management, and networking protocols. Your work focuses on the technical challenge of ensuring hardware functionality while optimizing for performance, power consumption, and energy efficiency.
What does a Design Verification Engineer earn?
Median $195800 from 78 postings across 10 companies.
Debug reasons for failed tests by analyzing waveforms and logs to pinpoint specific issues.
Review weekly failures to identify root causes and coordinate with designers to revise test cases.
Verify the RTL design of the GPU to ensure it is functionally correct and bug-free.
Develop and improve scripts to automate verification flows based on team requirements.
Collect and analyze test data to ensure full coverage of all design codes.
Create comprehensive verification plans based on provided architectural specifications.
Improve and optimize overall verification workflows through automation.
What we're looking for
Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
Experience designing at the register-transfer and logic levels of complex digital systems using modern modeling, simulation, synthesis, and verification tools.
Proficiency in using modern hardware description languages such as SystemVerilog.
Ability to address issues regarding performance, portability, and robustness in system design.
Understanding of systems-level issues including machine-level code, compiler optimization, computer arithmetic, memory management, and networking protocols.
Experience designing and implementing testing infrastructure for chips, including writing test vectors and performing lab testing.
Expertise in chip packaging specifications, test PCB design, fabrication, population, and lab instrument automation.
Experience designing and integrating hardware subsystems and co-designing hardware/software interfaces to meet performance, power, and cost objectives.
SystemVerilog
C
Python
Perl
Shell Scripting
Verilog
VCS
Verdi
MATLAB
Digital Electronics
RTL
Regression Automation
CPU Architecture
Functional Coverage
UVM
System Verilog
Python
C++
System C
SVA
Coverage Driven Verification
LLM
Prompt Engineering
RTL Simulation
4G/5G
3GPP
AXI
AHB
NoC
Bus Fabric
Perl
Automation