Design Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAFolsom, CAAustin, TX
Salary: $152,960–$229,440 / yr
Posted: 57 days ago
Freshness: Confirmed live yesterday
Closes: Aug 12, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $207k

This role $191k

$140k most similar roles pay here $250k

This role pays less than 51% of similar roles. Most pay $175,400–$239,462 — the shaded band above. At the midpoint, this role pays about $191k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 487 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 487 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer will join the team focused on cutting-edge server memory products to drive verification efforts for DDR interfaces, including advanced protocols such as DFI, DDR5, and LPDDR5/LPDDR6 across various DIMMs. The role involves developing and executing verification plans, comprehending PHY interactions within complete systems involving hardware, firmware, BIOS, and software, and engaging in cross-functional discussions with architects to plan and debug. Key responsibilities include contributing to verification methodology and supporting post-silicon teams for performance, power, and functional issues. The candidate must possess advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python or Perl. Technical skills required include building VIPs and BFMs from scratch, utilizing systemverilog assertions, constraints, coverage models, and formal verification methods to ensure memory interface functionality in server products.

What does a Design Verification Engineer earn in California?

Median $199724 from 60 postings across 7 companies.

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Skills

SystemVerilog UVM DDR5 LPDDR5 DFI C++ Python Perl RTL Formal Verification GLS NLP XPROP Assertion Functional Coverage Firmware BIOS Silicon

What you'll do

Drive verification efforts for DDR5, LPDDR5, and DFI memory systems in server products.
Develop and implement SystemVerilog and UVM based testbenches and functional coverage models.
Ensure hardware, firmware, BIOS, and software are aligned to enable all memory interface features.
Engage in cross-functional discussions with architects and designers for planning and debugging.
Build VIPs and BFMs for memory interfaces from scratch.
Support Post-Si teams in resolving product performance, power, and functional issues.
Contribute to the development of verification methodologies and share knowledge with the team.

What we're looking for

Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python or Perl.
Experience in verification planning and execution for DDR5, LPDDR5, and DFI memory systems.
Ability to understand RTL and micro-architecture to engage in cross-functional discussions with architects and designers.
Capability to coordinate with hardware, firmware, and software teams to align system-level memory architecture.
Experience developing SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models (preferred).
Ability to build VIPs and BFMs for memory interfaces from scratch (preferred).
Experience with GLS, NLP, XPROP simulation, formal verification methods, and system verilog assertions (preferred).
Bachelor’s degree plus or Master’s degree plus experience in a related discipline (preferred).