This role pays more than
56%
of similar roles. Most pay
$175,400–$239,462
— the shaded band above.
At the midpoint, this role pays about
$208k
versus about
$207k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
487 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 487 roles with salary data.
As a Design Verification Engineer, you will join the team responsible for cutting-edge server memory products to drive verification efforts for DDR interfaces. You will develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems across various DIMMs. Your daily work involves comprehending PHY interactions within complete systems involving hardware, firmware, BIOS, and software to ensure all features are aligned. You will engage in cross-functional discussions with architects and design engineers regarding RTL and micro-architecture while supporting post-silicon teams for performance, power, and functional debugging. The role requires advanced proficiency in SystemVerilog, UVM, C/C++, Python, and Perl. You will build testbenches, simulation environments, and coverage models, potentially creating VIPs and BFMs from scratch. Experience with GLS, NLP, XPROP simulations, and formal verification methods is also highly valued for this role.
What does a Design Verification Engineer earn in California?
Median $199724 from 60 postings across 7 companies.
Develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
Build SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models.
Analyze PHY interactions across hardware, firmware, BIOS, and software to ensure feature alignment.
Engage in cross-functional discussions with architects and designers to plan and debug RTL and micro-architecture.
Develop VIPs and BFMs for memory interfaces from scratch.
Support post-silicon teams in debugging product performance, power, and functional issues.
Contribute to the development of verification methodologies and share knowledge with the team.
What we're looking for
Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python or Perl.
Experience in developing and implementing SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models (preferred).
Experience with advanced memory protocols including DFI, DDR5, and LPDDR5/LPDDR6 (preferred).
Ability to engage in cross-functional discussions regarding RTL and micro-architecture for planning and debug.
Proficiency in system verilog assertions, constraints, and coverage (preferred).
Experience with formal verification methods and tool usage beyond standard applications (preferred).
Experience building VIPs and BFMs for memory interfaces from scratch (preferred).
Bachelor’s or Master’s degree in a related discipline (preferred).