This role pays more than
56%
of similar roles. Most pay
$175,400–$239,462
— the shaded band above.
At the midpoint, this role pays about
$208k
versus about
$207k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
487 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 487 roles with salary data.
As a Design Verification Engineer, you will join the team responsible for cutting-edge server memory products to drive verification efforts for DDR interfaces. You will develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems while ensuring that firmware, BIOS, and software are aligned with hardware features. Your daily work involves engaging in cross-functional discussions regarding RTL and micro-architecture, contributing to verification methodologies, and supporting post-silicon teams with performance, power, and functional debugging. You will utilize SystemVerilog, UVM, C/C++, Python, and Perl to build testbenches, simulation environments, and functional coverage models. The role requires expertise in systemverilog assertions, constraints, and formal verification methods. You will also build VIPs and BFMs from scratch while navigating complex memory protocols across various DIMMs to solve critical integration issues within the server product domain.
What does a Design Verification Engineer earn in California?
Median $199724 from 60 postings across 7 companies.
Develop and execute verification plans for DDR5, LPDDR5, and DFI memory systems in server products.
Build SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models.
Ensure firmware, BIOS, and software are aligned to enable all features of the memory interface.
Engage in cross-functional discussions with architects and design engineers for planning and debugging.
Support Post-Si teams in resolving product performance, power, and functional issues.
Contribute to verification methodology through knowledge sharing and technical contributions.
Develop VIPs and BFMs for memory interfaces from scratch.
What we're looking for
Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python or Perl.
Experience in developing and implementing SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models (preferred).
Experience with DDR5, LPDDR5, and DFI memory systems for server products.
Ability to engage in cross-functional discussions regarding RTL and micro-architecture for planning and debug.
Proficiency in system verilog assertions, constraints, and coverage (preferred).
Experience with formal verification methods and tool usage beyond standard applications (preferred).
Experience with GLS, NLP, and XPROP simulation (preferred).
Bachelor’s degree plus or Master’s degree plus experience in a related discipline (preferred).