Design Verification Engineer

Amazon Inc

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Diego, CAAustin, TXRedmond, WA
Salary: $122,600–$170,000 / yr
Posted: 44 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $146k

$111k most similar roles pay here $232k

This role pays less than 82% of similar roles. Most pay $159,937–$216,250 — the shaded band above. At the midpoint, this role pays about $146k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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View all roles at Amazon Inc

At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

As a Design Verification Engineer on the sub-team responsible for digital chip SOCs, you will support the development of communication systems for Low Earth Orbit satellites and gateways. You will be responsible for implementing state-of-the-art verification environments to test RTL against reference Matlab or C models while developing detailed test plans, running regressions, and collecting coverage matrices. Your daily work involves validating ASIC implementations in Verilog and SystemVerilog, as well as performing system-level verification using test benches constructed with UVM. You will also build highly automated environments for regression runs and database management. The role focuses on the technical challenge of designing modems, high-speed interfaces, embedded processors, and DSP solutions within the latest CMOS generation technologies to solve complex wireless communication problems in a space environment without legacy constraints.

Skills

UVM SystemVerilog Verilog Matlab C System C Formal Verification RTL ASIC Digital Verification test bench CMOS DSP Communication Systems

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans and write tests for the design.
Run regressions and collect coverage matrices to report progress to the program.
Validate ASIC implementations using Verilog and SystemVerilog.
Perform system-level verification using test benches constructed with UVM.
Build a highly automated environment to run regressions and manage the database.

What we're looking for

Bachelor's degree in Electrical Engineering, Communications Engineering, Computer Science, or a related field.
2+ years of experience in verification, preferably in communication systems.
2+ years of experience using UVM.
Master's or Ph.D. degree in Electrical Engineering, Communications Engineering, or a related field.
3+ years of experience in digital verification, preferably in communication systems.
Experience with Matlab, System C, C, or model development and DV integration.
Familiarity with formal verification techniques and modem design verification.
Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.

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