High-Bandwidth Memory (HBM) System Validation Lead

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TX
Salary
$174,400–$261,600 / yr
Posted
21 days ago
Freshness
Confirmed live yesterday
Closes
Apr 4, 2027
Nearby
99+ roles within 25 mi

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Competitive pay

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Similar $218k
This role $218k
$156k $280k
below market most similar roles pay here above market

This role pays more than 52% of similar roles. Most pay $182,000–$253,625 — the blue band above. At the midpoint, this role pays about $218k versus about $218k for comparable roles.

Based on 240 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · High-Bandwidth Memory (HBM) System Validation Lead

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High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform) joins the System Validation & Emulation team to lead pre-silicon and post-silicon validation for next-generation AI accelerator platforms. You will define and execute validation strategies for custom HBM subsystems integrated with large-scale compute platforms, driving memory bring-up, performance characterization, stress validation, and reliability analysis. Key responsibilities include developing validation plans for training flows, power-state transitions, and error recovery while leading complex silicon debug for crashes and data corruption. You will utilize Python, C/C++, logic analyzers, and protocol analyzers to build scalable automation frameworks and telemetry tools. The role requires deep expertise in DDR4/DDR5/LPDDR5/LPDDR6, HBM technologies, memory controllers, PHY architectures, cache coherency, NoCs, and chiplet-based architectures to solve complex system-level hardware and software integration problems.

Skills

HBM DDR4 DDR5 LPDDR5 LPDDR6 Python C C++ Pre-silicon Validation Post-silicon Validation FPGA Logic Analyzers Protocol Analyzers NoC Chiplets ASIC Signal Integrity Power Integrity Firmware

What you'll do

  • Own the end-to-end HBM validation strategy from emulation through production silicon.
  • Develop comprehensive validation plans for memory initialization, training flows, and power-state transitions.
  • Drive pre-silicon and first-silicon memory bring-up and perform root-cause analysis of failures.
  • Validate interactions between HBM, AI accelerators, compute fabrics, cache hierarchy, and NoC infrastructure.
  • Develop scalable automation frameworks and telemetry tools for memory validation and performance monitoring.
  • Lead complex silicon debug efforts to analyze crashes, hangs, data corruption, and performance bottlenecks.
  • Create stress scenarios representing real-world AI workloads to ensure system reliability.

What we're looking for

  • BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 8+ years of experience in memory validation, silicon validation, or platform bring-up.
  • Bachelor's degree and 6+ years of experience in ASIC design, verification, validation, or integration.
  • Master's degree and 5+ years of experience in ASIC design, verification, validation, or integration.
  • PhD and 4+ years of experience in ASIC design, verification, validation, or integration.
  • Strong understanding of DDR4/DDR5/LPDDR5/LPDDR6, HBM, memory controllers, PHY architectures, and cache/coherency systems.
  • Experience with pre-silicon validation, FPGA platforms, and post-silicon bring-up.
  • Programming experience in Python, C/C++.
  • Experience with HBM2, HBM3, HBM3E, or advanced stacked-memory technologies (preferred).
  • Experience with AI accelerators, GPU, HPC, or server-class platforms (preferred).
  • Familiarity with NoCs, Chiplets, Coherent interconnects, SI, PI, and thermal characterization (preferred).

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