CPU SRAM Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$122,500–$183,700 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k
This role $153k
$107k most similar roles pay here $263k

This role pays less than 85% of similar roles. Most pay $175,000–$227,500 — the shaded band above. At the midpoint, this role pays about $153k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU SRAM Design Engineer

Role Posting Log in to save

As a CPU SRAM Design Engineer on the high performance CPU team, you will take full ownership of custom SRAM and Register File designs from schematic capture through analysis and model generation. You will develop custom digital circuits for high-speed and low-power memory applications while performing layout planning, functional verification, simulation, margin verification, and timing characterization. The role involves collaborating with CAD and Physical Design teams to resolve PPA challenges and contribute to modeling, DFT, and analysis flow development. Key technical requirements include experience with circuit simulation, Monte Carlo analysis, static timing analysis, and Verilog for memory logical models. You will utilize specialized tools such as NanoTime, Ansys EMIR analysis, ESP-CV, and Liberate power analysis while navigating advanced custom circuit implementations in FinFET and Nanosheet technology nodes to solve complex memory performance challenges.

Skills

SRAM Register File Verilog Circuit Simulation Monte Carlo Analysis Static Timing Analysis FinFET Nanosheet BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification

What you'll do

  • Design custom digital circuits for high-speed and low-power SRAM and Register File designs.
  • Perform schematic capture and oversee layout planning for memory components.
  • Execute functional verification and simulation to ensure circuit reliability.
  • Conduct timing characterization and margin verification for memory designs.
  • Generate all necessary deliverable collateral models through detailed analysis steps.
  • Collaborate with the Physical Design team to resolve memory PPA challenges.
  • Contribute to modeling, DFT features, and analysis flow development.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 5+ years of practical experience or a Master's degree with 3+ years of experience.
  • A PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field is an acceptable educational qualification.
  • Experience designing SRAM circuits and implementing advanced custom circuit designs for high-performance and low-power features.
  • Proficiency in industry standard custom design tools, flows, and schematic capture.
  • Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.
  • Knowledge of semiconductor device fundamentals and variation-aware simulation in FinFET and Nanosheet technology nodes.
  • Experience with memory layout designs, functional verification, and BIST or other DFT features.
  • Proficiency with tools such as NanoTime, Ansys EMIR analysis, ESP-CV, and Liberate power analysis.

Related searches

More CPU SRAM Design Engineer jobs CPU SRAM Design Engineer jobs in Austin All jobs at Qualcomm

More like this

Similar roles

Senior Staff Principal CPU SRAM Design Engineer

Qualcomm

Austin, TX 43 days ago $179,000–$268,400
SRAM Circuit Simulation Monte Carlo Analysis Static Timing Analysis Verilog BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification FinFET Nanosheet
10+ yrs exp
Save

SRAM Circuit Design Engineer

Apple Inc

San Diego, CA 41 days ago $175,000–$308,500
SRAM Circuit Design RTL SoC GDS DFT IR/EM Machine Learning Scripting Memory Hierarchy Cache Design Schematic Capture Simulation Verification Silicon Debug Nanometer Device Physics
10+ yrs exp
Save

SRAM Circuit Design Engineer

Apple Inc

Beaverton, OR 41 days ago
SRAM Circuit Design RTL SoC GDS DFT IR/EM Machine Learning Scripting Schematic Capture Simulation Verification Memory Hierarchy Cache Design Nanometer Device Physics
10+ yrs exp
Save

SRAM Circuit Design Engineer

Apple Inc

Santa Clara, CA 41 days ago $184,700–$324,800
SRAM Circuit Design RTL SoC GDS DFT IR/EM Machine Learning Scripting Memory Hierarchy Cache Design Schematic Capture Silicon Debug Nanometer Device Physics
10+ yrs exp
Save

Senior SRAM Engineer

Nvidia

Remote 18 days ago $196,000–$310,500
SRAM Circuit Design Cadence Virtuoso SPICE Verilog Python Perl Shell Static Timing Analysis EM IR Analysis Formal Functional Verification Layout
10+ yrs exp Remote
Save