CPU Integration & 3DIC CAD Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$175,600–$263,400 / yr
Posted
49 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k
This role $220k
$137k $277k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $162,000–$227,500 — the blue band above. At the midpoint, this role pays about $220k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$218,400 across 552 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU Integration & 3DIC CAD Engineer

Role Posting Log in to save

The CPU Integration & 3DIC CAD Engineer joins the Nuvia/CPU team to build and support implementation tools and flows for custom CPUs. The role focuses on ensuring industry-leading power, performance, and area by enabling 3DIC and multi-die integration within existing or new flows. Key responsibilities include planning flows for TSVs during floor planning, supporting static timing and extraction across multiple dies, and managing power integrity flows across various chiplets. The engineer will architect, maintain, and support these flows while collaborating with EDA vendors to define roadmaps and resolve tool issues. Required technical skills include experience with Innovus, Primetime, or Star-RC, as well as advanced technology nodes at 5nm or lower. Proficiency in Python and Tcl for programming and data structures is also preferred.

Skills

Python Tcl Innovus Primetime Star-RC 3DIC Power Integrity Floor Planning Data Structures CAD Hardware Engineering

What you'll do

  • Build and support implementation tools and flows for custom CPUs.
  • Enable 3DIC and multi-die flows for implementation and planning.
  • Support static timing and extraction across multiple dies.
  • Support power integrity flows across multiple chiplets.
  • Architect, maintain, and support existing and new design flows.
  • Resolve project-specific issues related to CPU design and CAD flows.
  • Work with EDA vendors to define roadmaps and resolve tool issues.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of relevant engineering work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant engineering work experience.
  • Total of 8 years of combined educational and industry experience.
  • Ten+ years of hands-on experience in development of high-performance chips in a design or CAD role (preferred).
  • Experience with Innovus, Primetime, Star-RC, or equivalents (preferred).
  • Experience with advanced technology nodes of 5nm or lower (preferred).
  • High level of programming proficiency in Python and Tcl and knowledge of data structures (preferred).

Related searches

More CPU Integration & 3DIC CAD Engineer jobs CPU Integration & 3DIC CAD Engineer jobs in Santa Clara All jobs at Qualcomm

More like this

Similar roles

CPU Integration CAD Engineer

Qualcomm

Santa Clara, CA +1 49 days ago $175,600–$263,400
Python Tcl Innovus Calibre Physical Design Floorplanning DRC LVS place-and-route Timing Sign-off Data Structures Algorithms Automation Power Planning Pin Placement
4+ yrs exp
Save

CPU Synthesis CAD Engineer

Qualcomm

Santa Clara, CA +2 49 days ago $209,300–$313,900
Synthesis Place-and-Route Tcl Python Cadence Genus Synopsys Fusion Compiler LEC UPF Front-end Signoff Computer Architecture Logic Design Circuits Physical Design Automation
6+ yrs exp
Save

CPU STA CAD Engineer

Qualcomm

Santa Clara, CA +2 34 days ago $209,300–$313,900
Static Timing Analysis (STA) Python Tcl CI/CD ECO Synthesis PnR Test Driven Development AI
6+ yrs exp
Save

CPU Physical Design and Integration Engineer

Apple Inc

Santa Clara, CA 49 days ago $150,400–$277,600
Place and Route Physical Design DRC LVS STA EMIR CMOS Python Perl Tcl floor planning Layout Design PDV Clock Design Tapeout IP Integration
3+ yrs exp
Save

CPU Full Chip Physical Integration Engineer

Apple Inc

Austin, TX 49 days ago
Physical Design Place and Route Floorplanning EMIR DRC LVS STA Formal Verification Power Grid TCL Perl RedHawk Calibre Conformal LP LEC CMOS DFM SIGEM Layout Design Computer Architecture
3+ yrs exp
Save