CPU Integration & 3DIC CAD Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$175,600–$263,400 / yr
Posted
3 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $220k
$142k most similar roles pay here $276k

This role pays more than 72% of similar roles. Most pay $170,750–$227,350 — the shaded band above. At the midpoint, this role pays about $220k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 615 open roles on FindRole.

Listed pay typically runs $155,400–$232,600 across 593 roles with salary data.

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At a glance

TL;DR · CPU Integration & 3DIC CAD Engineer

As a CPU Integration & 3DIC CAD Engineer on the Nuvia/CPU team, you will build and support implementation tools and flows to ensure custom CPUs achieve industry-leading power, performance, and area. Your daily responsibilities include collaborating with cross-functional design and CAD teams to enable 3DIC and multi-die integration within existing or new flows. You will manage specific tasks such as TSV planning during floor planning, static timing and extraction across multiple dies, and power integrity flows for chiplets. Additionally, you will architect, maintain, and support these flows while working with EDA vendors to resolve tool issues and define roadmaps. The role requires proficiency in Python and Tcl, experience with advanced technology nodes like 5nm or lower, and familiarity with tools such as Innovus, Primetime, or Star-RC to solve complex multi-die integration challenges.

What you'll do

  • Build and support implementation tools and flows for custom CPU designs.
  • Enable 3DIC and multi-die technologies in existing and new design flows.
  • Manage planning flows including TSV integration during floor planning.
  • Support static timing and extraction across multiple dies.
  • Support power integrity flows across various chiplets.
  • Architect, maintain, and support technical flows while resolving project-specific issues.
  • Collaborate with EDA vendors to define roadmaps and resolve tool issues.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ years of experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of experience.
  • A total of 8 years of combined educational and industry experience.
  • Ten plus years of hands-on experience in development of high-performance chips in a design or CAD role (preferred).
  • Experience with Innovus, Primetime, Star-RC, or equivalent tools (preferred).
  • Experience with advanced technology nodes at 5nm or lower (preferred).
  • High level of programming proficiency in Python and Tcl and knowledge of data structures (preferred).

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