CPU Integration CAD Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$167,100–$250,700 / yr
Posted
38 days ago
Closes
Nov 4, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $209k
$140k most similar roles pay here $263k

This role pays more than 62% of similar roles. Most pay $169,625–$225,525 — the shaded band above. At the midpoint, this role pays about $209k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU Integration CAD Engineer

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As a CPU Integration CAD Engineer at Qualcomm Technologies, Inc., you will join the NUVIA team to build and support industry-leading implementation tools and flows for custom CPUs, ensuring they achieve top-tier power, performance, and area metrics. Your daily tasks include collaborating with cross-functional teams such as physical design, SOC integration, and EDA vendors to develop and integrate floorplanning methodologies and PDV analysis tools. You will also maintain and resolve issues within implementation flows while defining roadmaps for EDA tool improvements. Ideal candidates have over ten years of experience in high-performance chip development, strong programming skills in Python and Tcl, and hands-on knowledge with PNR tools like Innovus or Calibre PDV, as well as a range of physical design tasks across advanced technology nodes.

Skills

Python Tcl Innovus Calibre Docker CI/CD Git Unix/Linux Perl C++ VLSI Physical_Design EDA Advanced_Technology_Nodes Place_and_Route Timing_Sign-off PDV_Analysis

What you'll do

  • Develop and integrate flows for floorplanning and PDV analysis.
  • Resolve project-specific issues in implementation flows.
  • Collaborate with EDA vendors to define tool roadmaps.
  • Maintain and support high-performance chip design tools.
  • Automate processes using Python, Tcl, and other scripting languages.
  • Conduct physical design tasks including place-and-route and timing sign-off.

What we're looking for

  • Ten+ years of hands-on experience in high-performance chip development.
  • Proficiency in Python and Tcl for scripting and automation.
  • Expertise with PNR tool Innovus or PDV Calibre tool.
  • Experience across various Physical Design tasks including place-and-route, analysis, timing sign-off, and PDV.
  • Strong background in advanced technology nodes (5nm or lower).
  • Bachelor’s/Master’s degree in Electrical/Electronics Engineering or Computer Science.

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