CPU Integration CAD Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$175,600–$263,400 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $220k
$137k $277k
below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $162,000–$231,150 — the blue band above. At the midpoint, this role pays about $220k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Integration CAD Engineer

The CPU Integration CAD Engineer joins the CPU Engineering group to build and support world-class implementation tools and flows. This role focuses on ensuring custom CPUs achieve industry-leading power, performance, and area. The engineer will develop, integrate, and release methodologies for floorplanning, including power planning and pin placement, as well as PDV analysis such as DRC, LVS, and antenna checks. Key responsibilities include architecting and maintaining implementation flows, resolving project-specific issues, and collaborating with EDA vendors to define roadmaps. Candidates must possess programming proficiency in Python and Tcl, knowledge of data structures and algorithms, and experience with automation. Technical requirements include familiarity with Innovus PNR tools, Calibre PDV tools, and physical design tasks like place-and-route, timing sign-off, and advanced technology nodes at 5nm or lower.

What you'll do

  • Build and support implementation tools and flows for custom CPU designs.
  • Develop and release flows for floorplanning, power planning, and pin placement.
  • Create methodologies for Physical Design Verification (PDV) analysis including DRC, LVS, and antenna.
  • Architect and maintain implementation flows to resolve project-specific issues.
  • Coordinate with EDA vendors to define roadmaps and resolve tool-related issues.
  • Automate physical design tasks using Python and Tcl.
  • Execute physical design tasks ranging from place-and-route to timing sign-off.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of relevant engineering experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant engineering experience.
  • Ten+ years of hands-on experience in development of high-performance chips in a design or CAD role (preferred).
  • High level of programming proficiency in Python and Tcl, including knowledge of data structures and algorithms (preferred).
  • Experience with automation (preferred).
  • Strong user of PNR tool Innovus, PDV Calibre tool, or equivalent (preferred).
  • Experience with advanced technology nodes of 5nm or lower (preferred).

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