CPU Integration CAD Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$167,100–$250,700 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Closes
Jan 26, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $209k
$138k most similar roles pay here $263k

This role pays more than 60% of similar roles. Most pay $161,787–$222,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · CPU Integration CAD Engineer

As a CPU Integration CAD Engineer within the CPU Engineering group, you will build and support implementation tools and flows to ensure custom CPUs achieve industry-leading power, performance, and area. You will work with cross-functional teams to develop, integrate, and release methodologies for floorplanning, including power planning and pin placement, as well as PDV analysis such as DRC, LVS, and antenna checks. Your daily responsibilities include architecting and maintaining implementation flows, resolving project-specific issues, and collaborating with EDA vendors to define roadmaps and resolve tool problems. The role requires proficiency in Python and Tcl, knowledge of data structures and algorithms, and experience with automation. You will utilize tools like Innovus or Calibre while working on advanced technology nodes at 5nm or lower to solve complex physical design challenges for high-performance chips.

What you'll do

  • Build and support implementation tools and flows for custom CPU designs.
  • Develop and release methodologies for floorplanning, including power planning and pin placement.
  • Create and maintain workflows for physical design verification (PDV) analysis such as DRC, LVS, and antenna.
  • Architect and maintain implementation flows while resolving project-specific technical issues.
  • Collaborate with EDA vendors to define product roadmaps and resolve tool-related problems.
  • Automate complex tasks using Python and Tcl scripts.
  • Optimize CPU designs for industry-leading power, performance, and area metrics.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • At least 4 years of experience for Bachelor's holders, 3 years for Master's holders, or 2 years for PhD holders in relevant engineering fields.
  • Ten or more years of hands-on experience in high-performance chip development in a design or CAD role.
  • High level of programming proficiency in Python and Tcl with knowledge of data structures and algorithms.
  • Experience with automation and advanced technology nodes at 5nm or lower.
  • Proficiency with PNR tools like Innovus, PDV tools like Calibre, or equivalent technologies.

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