CPU Synthesis CAD Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$198,700–$298,100 / yr
Posted
7 days ago
Closes
Dec 16, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $248k
$130k most similar roles pay here $316k

This role pays more than 89% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $248k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 807 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 487 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU Synthesis CAD Engineer

As a CPU Synthesis CAD Engineer at Qualcomm Technologies, Inc., you will join a team of top-tier engineers dedicated to reimagining silicon and developing cutting-edge computing platforms. Your role involves architecting and implementing new features in high-performance synthesis CAD flows, recommending methodology improvements for optimal power, performance, and area, and collaborating with global physical design teams to provide synthesis guidance. You will also work closely with EDA vendors to address tool issues and define roadmaps. Ideal candidates have over eight years of experience in chip synthesis and place-and-route, proficiency in Tcl and Python, and expertise with advanced technology nodes and leading-edge synthesis tools like Cadence Genus or Synopsys Fusion Compiler. This role demands a deep understanding of computer architecture and micro-architecture, as well as the ability to solve complex problems independently while collaborating across functions.

What you'll do

  • Develop and integrate new features in high-performance synthesis CAD flow.
  • Recommend and implement methodology improvements for optimal power, performance, and area.
  • Maintain and debug synthesis and implementation flows to resolve specific project issues.
  • Provide synthesis methodology guidance to worldwide CPU physical design teams.
  • Collaborate with EDA vendors to define roadmaps and address tool-related challenges.

What we're looking for

  • 8+ years of hands-on experience in synthesis and place-and-route for high-performance chips.
  • Proficient in Tcl and Python for automation and scripting.
  • Experience with logic and physical synthesis, LEC, UPF, and front-end signoff at advanced technology nodes (5nm or lower).
  • Strong user of Cadence Genus or Synopsys Fusion Compiler for synthesis tooling.
  • Proven ability to manage and regress synthesis flows in complex design environments.
  • Collaborative problem-solving skills with cross-functional teams on CPU designs.

More like this

Similar roles

CPU Integration CAD Engineer

Qualcomm

Santa Clara, CA +1 7 days ago $167,100$250,700
Python Tcl Innovus Calibre Docker CI/CD Git Unix/Linux Perl C++ VLSI Physical_Design EDA Advanced_Technology_Nodes Place_and_Route Timing_Sign-off PDV_Analysis

CPU SRAM Design Engineer

Qualcomm

Austin, TX 24 days ago $122,500$183,700
SRAM Register_File Circuit_Simulation Monte_Carlo_Analysis Static_Timing_Analysis NanoTime Ansys_EMIR_analysis ESP-CV Liberate_power_analysis Verilog BIST DFT Custom_Memory_Layout Physical_Implementation_Impact Timing_Characterization

GPU Design Implementation Engineer(Synthesis)

Qualcomm

Austin, TX 39 days ago $133,600$200,400
Synopsys Tcl Perl Python CMOS VLSI EDA ASIC FINFETs GAA RTL PrimeTime Conformal LEC Formality Sub-micron technology Physical design implementation Scripting Debugging Analytical skills

Physical Design Engineer - DSP Team

Qualcomm

Austin, TX 79 days ago $164,000$246,000
Synopsys_Fusion_Compiler Synopsys_ICC2 Cadence_Genus Cadence_Innovus Python Perl TCL Shell_Scripting Timing_Analysis Physical_Design Clock_Tree_Synthesis Power_Optimization Logic_Optimization ASIC_Physical_Design CI/CD

Principal CPU Physical Design Engineer (San Diego, CA)

Qualcomm

San Diego, CA 16 days ago $211,900$317,900
TCL Python Synopsys Cadence RTL-to-GDSII ASIC SoC Physical Design Timing Closure Power Optimization EDA STA Signoff Place & Route Scripting Advanced Nodes PPA Trade-offs CPU Design Challenges Data-Driven Debugging