Circuit Design Engineer, Library

Apple Inc

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Work type
On-site
Location
Beaverton, OR
Posted
67 days ago
Freshness
Confirmed live today

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Similar $201k
$137k $243k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,000–$233,050.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · Circuit Design Engineer, Library

The Circuit Design Engineer - Library will join the Digital Design Engineering group as a Circuit Design Engineering Lead. In this role, you will lead a custom digital circuits team and library development for state-of-the-art ASICs and processor designs. Your daily responsibilities include driving the development of high-performance, low-power optimized standard cells, level shifters, and retention designs to improve PPA. You will engage with CPU, SOC, and GPU teams on chip-level integration, perform circuit QA checks, and manage migrations to new PDKs. Required skills include experience with standard cell circuit development, Virtuoso, DRM, DRC/LVS decks, and PDV flows. You must also possess knowledge of circuit robustness analysis and experience scripting in Perl and/or TCL to support advanced tech node device behavior.

What you'll do

  • Drive development of high-performance, low-power optimized standard cells to improve design PPA.
  • Develop optimal level shifters and retention designs to meet low-power requirements.
  • Identify and implement next-generation ideas to further improve PPA.
  • Coordinate with CPU, SOC, and GPU teams on chip-level integration requirements.
  • Drive circuit QA checks and develop new methodologies based on design requirements.
  • Work with foundries on DRM compliant layout checkers and iPDK requirements.
  • Manage migration to new PDKs, including PDV of standard cells and releases.

What we're looking for

  • Minimum of 3 years of experience.
  • 3+ years of experience in Standard cells circuit development (preferred).
  • Proven experience in developing, driving, and implementing circuit methodologies (preferred).
  • Proven experience leading and mentoring a small team (preferred).
  • Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, and Virtuoso (preferred).
  • Design experience in advanced tech node device behavior with understanding of layout rules (preferred).
  • Design experience in flop, complex Standard Cells design, and Power Management Cells (preferred).
  • Bachelor's Degree.

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