Custom Library Design Lead

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 32 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k

This role $242k

$125k $328k

below market most similar roles pay here above market

This role pays more than 80% of similar roles. Most pay $169,242–$231,300 — the blue band above. At the midpoint, this role pays about $242k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Custom Library Design Lead

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The Custom Library Design Lead joins the Digital Design Engineering group to lead a custom circuits team in developing state-of-the-art ASICs. This role involves leading and mentoring a small team of circuit design engineers to drive the design, development, and characterization of high-performance, low-power standard cells and power management cells. Key responsibilities include improving chip design PPA, managing migrations to new PDKs, and driving layout dependent design optimization. The position requires expertise in standard cell layout, DRM, DRC/LVS decks, PDV flows, and Virtuoso. Candidates must understand advanced tech node device behavior and layout rules. The role specifically addresses the technical challenge of integrating new ideas into SOC design efforts to meet low-power product requirements and cellular library needs.

Skills

ASIC Virtuoso DRC LVS PDK PDV Layout Dependent Design Power Management Cells SOC Design Digital Design Circuit Design Agentic Flows

What you'll do

Lead and mentor a small team of circuit design engineers while providing technical guidance.
Drive the design, development, and characterization of high-performance, low-power standard cells to improve PPA.
Develop power management cell designs that meet specific low-power product requirements.
Identify and implement new ideas to drive PPA improvements and chip-level integration.
Drive library checks, analysis, and the development of new design methodologies.
Coordinate with foundries on technology requirements, layout-dependent design optimization, and layout checks.
Manage the migration to new PDKs and oversee the PDV of standard cells and releases.
Define and support cellular library requirements by engaging with cellular teams to understand specific design needs.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Master's Degree (preferred).
10+ years of experience in Standard cells library development (preferred).
Proven experience in developing, driving, and implementing design methodologies (preferred).
Proven experience leading and mentoring a small team (preferred).
Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, and Virtuoso (preferred).
Design experience in advanced tech node device behavior with understanding of layout rules (preferred).
Design experience in flop, complex Standard Cells design, and Power Management Cells (preferred).

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