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Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Posted: 29 days ago
Closes: Nov 4, 2026
Nearby: 99+ roles within 25 mi

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Similar $194k

$143k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $165,250–$222,000.

Based on 240 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 270 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 196 roles with salary data.

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TL;DR · Careers

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Qualcomm Technologies is seeking a Senior ASIC Design Engineer to join its Next Generation High-Speed Memory and Cache Controller team, focusing on developing advanced memory subsystems for high-speed HBM/LPDDR/DDR interfaces in QCT products. The role involves architecture definition, RTL coding, and deployment of next-generation memory controllers interfacing with CPUs, GPUs, DSPs, and multimedia processors at gigahertz speeds. Key responsibilities include designing micro-architectures, implementing RTL code, collaborating with verification engineers, debugging designs, and supporting physical design tasks such as synthesis, timing closure, and power analysis. Ideal candidates have 5+ years of ASIC design experience, a strong background in hardware architecture, and expertise in LPDDR memory controllers, NoC-based architectures, and x86 or ARM CPU/bus systems.

Skills

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification

What you'll do

Develop architecture and design specifications for high-speed memory subsystems.
Implement RTL code for next-generation memory controllers and cache systems.
Collaborate with verification engineers to ensure high-quality designs are delivered.
Debug complex logic designs and provide support during chip integration phases.
Conduct synthesis, timing closure, and physical design support tasks efficiently.
Perform gate-level simulations and power analysis on memory subsystems.

What we're looking for

5+ years of ASIC design and RTL coding experience
3+ years of hardware architecture experience
Experience with LPDDR memory and cache controller designs
Familiarity with NoC based architectures and front-end interfacing to CPUs/DSPs
Knowledge of HBM memory type designs and on-chip SRAM/L3 cache controllers
Understanding of x86 or ARM CPU/bus architectures
Ability to debug high-speed (1GHz+) designs in QCT products

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