As a senior RTL designer on Qualcomm Atheros' Integrated Wireless Technology team, you will be responsible for micro-architecture, RTL design, and development of new functional blocks, as well as subsystem and full-chip integration through the complete ASIC lifecycle from concept to tape-out. You will collaborate closely with other subsystem teams to ensure smooth integration while interfacing with verification, DFT, FPGA emulation, and implementation teams. The role requires expertise in SoC micro-architecture, multi-domain clocking implementation, design linting, CDC analysis, AMBA bus protocols, Python/Perl scripting, and a solid understanding of AI/ML-based design methodologies. Experience with ARM CoreSight architecture, AXI Bus protocol, PCIe, USB peripheral subsystems, low power design, and chip interconnect (NOC) is highly valued in this fast-paced environment focused on cutting-edge WiFi technology and SOC infrastructure.
Verilog
System-Verilog
Python
Perl
Tcl
Makefiles
CDC checks
Formal equivalence
RTL design
Synthesis
Timing analysis
DFT
ATE test development
Post-si bringup
Debugging
Behavioral real number modeling
Mixed signal design
Custom designed IPs
Agentic AI flows