ASIC Implementation Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $120,000–$192,000 / yr
Posted: 40 days ago
Closes: Oct 24, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $156k

$108k most similar roles pay here $233k

This role pays less than 78% of similar roles. Most pay $159,937–$216,250 — the shaded band above. At the midpoint, this role pays about $156k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · ASIC Implementation Engineer

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Broadcom is seeking a Physical Design Engineer with extensive expertise to join its ASIC Products Division, focusing on advancing next-generation AI designs. This role involves executing physical design tasks such as place and route, clock tree synthesis, floor planning, and timing closure, while also developing methodologies and collaborating closely with RTL engineers. The ideal candidate will possess deep knowledge in EM/IR analysis and top-level STA, along with experience in custom clock trees and insertion reduction techniques. Proficiency in TCL/Perl scripting and familiarity with EDA tools are essential, as is the ability to manage a full physical design cycle from RTL to tape-out. This position requires strong communication skills and hands-on work at Broadcom’s San Jose site.

Skills

TCL PERL EDA Tools RTL Verilog Physical Design Place and Route Clock Tree Synthesis Floor-planning Layout Timing Closure EM/IR Analysis

What you'll do

Execute Physical Design, Verification, and Timing Closure for AI designs.
Perform EM/IR Analysis to ensure design reliability.
Conduct Place and Route operations efficiently.
Develop custom clock trees with insertion reduction techniques.
Lead top-level floorplanning and layout processes.
Create methodologies and flows for physical design cycles.
Collaborate closely with IC Design RTL Engineers on projects.

What we're looking for

At least 8 years of experience in physical design for ASICs.
Expertise in Physical Design, including Place and Route, Floor-planning, and Layout.
Proficiency in Timing Closure, Clock Tree Synthesis, and EM/IR Analysis.
Strong scripting skills with TCL and PERL.
Experience with EDA tools throughout the full physical design cycle.
Excellent communication skills for collaboration with RTL Engineers.

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