ASIC Implementation Engineer

Broadcom

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $120,000–$192,000 / yr
Posted: 137 days ago
Freshness: Confirmed live yesterday
Closes: Oct 24, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $156k

$107k most similar roles pay here $243k

This role pays less than 82% of similar roles. Most pay $168,500–$216,562 — the shaded band above. At the midpoint, this role pays about $156k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer

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The ASIC Implementation Engineer joins the ASIC Products Division to drive next-generation AI designs using advanced technology. This role focuses on the full physical design cycle, taking a Netlist through to silicon tape-out. Key responsibilities include executing Physical Design, Physical Verification, and Timing Closure using various strategies. The engineer will perform top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis, floor-planning, and layout tasks while collaborating with IC Design RTL Engineers. To succeed in this role, the candidate must possess proficiency in TCL and PERL scripting alongside expertise in related EDA tools. The position addresses critical technical challenges in high-performance semiconductor design, specifically focusing on custom clock trees, insertion reduction, and skew balancing techniques to ensure successful tape-out for complex AI hardware products.

Skills

Physical Design STA Floorplanning Layout Clock Tree Synthesis EM/IR Analysis TCL Perl EDA Tools RTL Tape-out

What you'll do

Execute the full physical design cycle from netlist to silicon tape-out.
Perform physical verification and timing closure using various methods and strategies.
Conduct top-level STA, EM/IR analysis, and Place and Route Clock Tree Synthesis.
Implement custom clock trees with insertion reduction and skew balancing techniques.
Execute floorplanning and layout for complex ASIC designs.
Develop flow and methodology for physical design processes.
Write TCL and PERL scripts to automate tasks in EDA tools.

What we're looking for

Bachelor's degree in Electrical Engineering or Electronics Engineering.
8+ years of relevant experience.
Expertise in the full physical design cycle from Netlist to silicon tape-out.
Proficiency in TCL and PERL scripting.
Experience with Physical Verification and Timing Closure.
Experience with top-level STA, EM/IR Analysis, and Place and Route Clock Tree Synthesis.
Experience with floorplanning and layout methodology development.
Excellent verbal and written communication skills.

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