Design Verification Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 43 days ago
Freshness: Confirmed live yesterday
Closes: Jan 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $144k

$102k most similar roles pay here $238k

This role pays less than 88% of similar roles. Most pay $168,000–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The ASICS Design Verification Engineer joins the ASICS Engineering team to manage the complete verification lifecycle from system-level concept through tape out and post-silicon support. This role focuses on comprehensive pre-silicon test planning for digital power IPs, including testbench development using SystemVerilog-UVM, coverage development, assertion model development, and formal verification property checking. The engineer will also learn and deploy power-aware UPF verification flows while developing automation to improve overall verification efficiency. Key technical requirements include proficiency in SystemVerilog, Verilog or VHDL, and C or C++ programming. Candidates should possess skills in Perl or Python scripting and knowledge of AMBA Bus protocols like AXI, AHB, and APB. The role addresses the critical challenge of ensuring functional integrity and power awareness within complex digital power integrated circuit designs.

Skills

SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation

What you'll do

Perform comprehensive pre-silicon test planning for digital power IPs.
Develop testbenches using SystemVerilog and UVM methodologies.
Create coverage models and assertion models for verification.
Execute formal verification through property checking.
Deploy power-aware UPF verification flows and methodologies.
Develop automation tools to improve overall verification efficiency.
Manage the complete verification lifecycle from system-level concept to post-silicon support.

What we're looking for

Bachelor's degree in Engineering, Science, or a related field.
Master's degree in Computer Science, Electrical Engineering, or a related field.
PhD in Science, Engineering, or a related field.
2+ years of experience with ASIC design and verification tools, techniques, and methodology.
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals and C/C++ programming skills.
6+ years of experience with verification methodologies like UVM or OVM and assertion-based formal verification.
6+ years of experience with scripting and automation using Perl or Python.

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