ASIC Design Verification Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$178,400–$267,600 / yr
Posted
86 days ago
Freshness
Confirmed live yesterday
Closes
Jun 17, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k
This role $223k
$127k most similar roles pay here $283k

This role pays more than 81% of similar roles. Most pay $162,000–$215,475 — the shaded band above. At the midpoint, this role pays about $223k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC Design Verification Engineer

The ASIC Design Verification Engineer joins the MSIP UMC team to develop leading-edge DDR technologies powering data center and machine learning workloads. This role involves all aspects of IP verification, including creating verification architectures, defining test plans, developing environments, and achieving coverage closure for complex IP blocks. The engineer will collaborate with architects to shape cutting-edge verification methodologies while taking ownership of key features across multiple projects. Day-to-day tasks include triaging regressions, analyzing functional coverage, conducting code reviews, and reproducing post-silicon bugs in dynamic simulation or formal environments. Required skills include proficiency in SystemVerilog, UVM, SystemC, Verilog, C/C++, and OOP within Linux and Windows environments. The role requires a strong understanding of digital design, computer architecture, and constrained random verification to ensure high-quality performance for client, server, embedded, graphics, and semi-custom chips.

What you'll do

  • Develop verification architectures, methodologies, and development plans in collaboration with IP architects.
  • Take end-to-end ownership of key features and verify complex IP blocks across multiple projects.
  • Create and maintain test plans, verification environments, regressions, and coverage closure.
  • Develop and maintain VIPs, libraries, and test cases using SystemVerilog, UVM, and SystemC.
  • Triage and debug regression failures to ensure functional integrity.
  • Analyze code and functional coverage to achieve verification sign-off.
  • Reproduce post-silicon functional bugs within dynamic simulation or formal verification environments.
  • Develop scripts and tools to improve engineering infrastructure and execution efficiency.

What we're looking for

  • Hold a BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.
  • Possess experience in ASIC design verification and digital design.
  • Demonstrate a strong understanding of computer architecture and block-level constrained random verification.
  • Proficiency in Verilog, SystemVerilog, C/C++, UVM, and Object-Oriented Programming (OOP).
  • Ability to debug SystemVerilog RTL code using simulation tools.
  • Experience with formal verification is considered an asset.
  • Ability to work in both Linux and Windows environments.
  • Strong analytical thinking, problem-solving skills, and attention to detail.

More like this

Similar roles

ASIC Verification Engineer

Nvidia

Austin, TX 9 days ago $116,000$189,750
SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Design Automation Scripting Coverage-based Verification
2+ yrs exp Hybrid

ASIC Design Verification Engineer

Cisco

Remote (San Jose, CA) 53 days ago $165,000$241,400
System Verilog UVM ASIC Design C C++ Python Perl Linux Formal Verification Networking Post-silicon Lab Bring-up
7+ yrs exp Remote

ASIC Verification Engineer

Nvidia

Santa Clara, CA 9 days ago $116,000$189,750
System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics Object-Oriented Programming Automation Scripting ASIC Design Verification
3+ yrs exp Hybrid

ASIC Design Verification Engineering Leader

Cisco

Remote (San Jose, CA) 38 days ago $214,100$309,800
SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4
10+ yrs exp Remote

ASIC Verification Engineer

Broadcom

Irvine, CA 14 days ago
SystemVerilog UVM Verilog VHDL C++ Python Perl TCL Ethernet ASIC Verification Logic Design Computer Architecture Object-Oriented Programming Scripting
3+ yrs exp

Senior ASIC Verification Engineer

Nvidia

Austin, TX 9 days ago $136,000$218,500
System Verilog UVM RTL Verilog Python VCS Verdi Computer Architecture Functional Coverage Scripting ASIC Verification Simulation Tools
3+ yrs exp