ASIC STA Technical Lead

What you'll do

• Lead the DFT and quality process through the entire implementation flow and post-silicon validation phases.
• Perform Static Timing Analysis (STA) for ASIC designs with a focus on timing constraints like clock groups and exceptions.
• Develop and verify timing constraints using SDC files.
• Debug and analyze complex timing issues, including scan shift/capture, BIST, and PCIe or memory constraints.
• Manage physical design signoff activities for next-generation networking chips.
• Perform CDC/RDC and conformal verification to ensure signal integrity across clock domains.
• Utilize scripting languages like Python, TCL, or Perl to automate tasks and manage tools.
• Communicate complex timing data clearly to cross-functional teams during the development process.

What we're looking for

• Bachelor's degree plus 8 years of experience, Master's plus 6 years, or PhD plus 3 years of related experience.
• Experience with RTL design, CDC/RDC and conformal verification, and SDC development.
• Experience in timing constraint development and verification.
• Proficiency in at least two of the following scripting languages: Perl, TCL, Python, or Makefile.
• Master's degree plus 15+ years of experience (preferred).
• Experience debugging and analyzing PCIe timing constraints and TSMC memory timing constraints (preferred).
• Experience with SDC debugging, STA tools like Synopsys TCM/Primetime, and synthesis tools like Synopsys Fusion/design Compiler (preferred).
• Experience with Tessent tool for DFT insertion in RTL or analyzing timing closure of DFT modes (preferred).