Senior ASIC Physical Design Engineering Technical Lead

Cisco

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CAAustin, TX
Salary: $214,100–$309,800 / yr
Employment: Full-time
Posted: 3 days ago
Freshness: Confirmed live today
Closes: Dec 1, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k

This role $262k

$136k $328k

below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $177,250–$223,000 — the blue band above. At the midpoint, this role pays about $262k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 284 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 210 roles with salary data.

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At a glance

TL;DR · Senior ASIC Physical Design Engineering Technical Lead

Role Posting Log in to save

The Senior ASIC Physical Design Engineering Technical Lead joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves managing the RTL-to-GDSII implementation, including logic synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks. The lead will optimize performance and die-size while identifying efficiency gaps in tool flows and methodologies. Key responsibilities include guiding clock tree synthesis strategies, executing multi-mode sign-off processes, and performing functional and timing ECO implementations. The position requires expertise in 7nm, 5nm, and 3nm process technologies using EDA tools such as Innovus, Primetime, Tempus, Redhawk, Voltus, and Calibre. Candidates should also possess skills in Python, TCL, or Perl programming to support automation and design methodology.

Skills

RTL-to-GDSII Logic Synthesis Floorplanning Place and Route Static Timing Analysis Power Integrity Clock Tree Synthesis ECO Innovus Primetime Tempus Redhawk Voltus Calibre Python TCL Perl

What you'll do

Execute RTL-to-GDSII implementation including logic synthesis, floorplanning, place and route, and static timing analysis.
Optimize design performance and die-size through power integrity and equivalence checks.
Analyze existing tool flows to identify efficiency gaps and implement transformative enhancements.
Guide Clock Tree Synthesis strategies and provide actionable feedback to implementation teams.
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode and multi-corner scenarios.
Complete functional and timing ECO implementations using industry-standard flows and automation.
Evaluate various timing methodologies and tools across different technologies and design types.

What we're looking for

Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience.
Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience.
PhD in Electrical Engineering with 5+ years of Physical Design experience.
Experience working on Fullchip activities.
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
Experience with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.
Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis (preferred).
Experience with Python, TCL, or Perl programming (preferred).

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