ASIC Implementation Engineer STA

Broadcom

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
57 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 12, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $187k
$133k most similar roles pay here $240k

This role pays less than 53% of similar roles. Most pay $169,625–$223,000 — the shaded band above. At the midpoint, this role pays about $187k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer STA

The ASIC Implementation Engineer STA is responsible for ensuring that the ASIC meets performance targets and timing requirements across all operating conditions. The role involves owning full-chip timing sign-off, performing quality checks across various process, voltage, and temperature corners, and authoring, validating, and maintaining SDC constraints for functional and test modes like Scan, MBIST, and ATPG. You will manage multi-mode multi-corner analysis, implement ECOs to fix setup, hold, and transition violations, and collaborate with RTL, Physical Design, and DFT teams to resolve complex issues. The position requires expertise in Cadence or Synopsys tools and proficiency in Tcl, Python, Perl, or Shell for automating flows. Key technical focus areas include advanced concepts like AOCV/POCV, signal integrity, IR-drop aware STA, and balancing power, performance, and area goals during the chip implementation process.

What you'll do

  • Perform full-chip timing sign-off and quality checks across all process, voltage, and temperature corners.
  • Author, validate, and maintain SDC constraints for functional and test modes.
  • Incorporate foundry guidelines, margins, and derates into timing analysis flows.
  • Manage and analyze multi-mode multi-corner (MMMC) scenarios to ensure reliability.
  • Automate and implement ECOs to resolve setup, hold, and transition violations.
  • Develop scripts in Tcl, Python, or Perl to automate analysis flows and data mining.
  • Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues.
  • Analyze trade-offs between power, performance, and area goals for chip implementation.

What we're looking for

  • Bachelor's degree in Electrical Engineering or Computer Engineering.
  • Minimum of 12 years of hands-on experience in ASIC STA and timing constraints development.
  • Experience performing timing closure using Cadence or Synopsys tools.
  • Expertise in managing on-chip variation derates and optimizing multi-mode multi-corner constraints.
  • Proficiency in scripting languages including Tcl, Python, Perl, or Shell for automating analysis flows.
  • Strong problem-solving skills with attention to technical detail.
  • Excellent team collaboration and communication skills.

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