ASIC Implementation Engineer STA

What you'll do

• Perform full-chip timing sign-off and quality checks across all process, voltage, and temperature corners.
• Author, validate, and maintain SDC constraints for functional and test modes.
• Incorporate foundry guidelines, margins, and derates into timing analysis flows and methodologies.
• Manage and analyze hundreds of timing scenarios for Multi-Mode Multi-Corner (MMMC) analysis.
• Automate, generate, and implement ECOs to resolve setup, hold, and transition violations.
• Develop Tcl, Python, and Perl scripts to automate analysis flows and perform data mining.
• Analyze tradeoffs between power, performance, and area to drive chip implementation flows.

What we're looking for

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• Minimum of 12 years of hands-on experience in ASIC STA and timing constraints development.
• Experience in timing closure using Cadence or Synopsys tools.
• Experience managing on-chip variation derates and optimizing multi-mode multi-corner constraints.
• Proficiency in scripting languages including Tcl, Python, Perl, or Shell.
• Expert proficiency in industry-standard sign-off tools.
• Strong problem-solving skills with attention to every technical aspect.
• Clear and precise communication skills and ability to work as a team player.