ASIC Implementation Engineer PD

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$121,900–$195,000 / yr
Employment
Full-time
Posted
40 days ago
Freshness
Confirmed live today
Closes
Jan 12, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k
This role $158k
$108k $248k
below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $177,250–$227,300 — the blue band above. At the midpoint, this role pays about $158k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer PD

The ASIC Implementation Engineer PD joins the Asic Products Division to work on next generation Artificial Intelligence and PCIe Switch Products. This role requires in-depth expertise in all Physical Design aspects of taking RTL to silicon tape-out. Key responsibilities include owning chip floor planning, partition creation, clock tree delivery, and top level partition management. The engineer will resolve physical design issues related to chip integration and assembly while managing cross functional interactions for I/O and bump planning. The position involves developing floorplan implementation methodologies and performing technical evaluations of vendors and IP. Required skills include experience with Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, and chiplet technologies. Candidates must use Python, Tcl, or Perl scripting languages alongside various EDA tools.

What you'll do

  • Own chip floor planning, partition creation, and clock tree delivery for top level partitions.
  • Resolve physical design issues related to chip integration and assembly.
  • Manage cross-functional interactions regarding top level floorplanning, I/O, and bump planning with the package team.
  • Develop and improve floorplan implementation methodologies using industry and internal tools.
  • Perform technical evaluations of vendors and IP to provide recommendations meeting design specifications.
  • Resolve chip level DRC, LVS, and EMIR issues for advanced nodes.
  • Execute hierarchical floorplanning, power grid design, and top level pipeline planning.

What we're looking for

  • In-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
  • Experience in chip floor planning, partition creation, clock tree delivery, and I/O or bump planning.
  • Ability to resolve physical design issues related to chip integration, assembly, and DRC/LVS/EMIR issues for advanced nodes.
  • Experience in developing and improving floorplan implementation methodologies using industry and internal tools.
  • Experience in collaborating with design, package, and methodology teams during the development phase.
  • Bachelors degree in Electrical Engineering and 8+ years of experience in top level floorplanning (preferred).
  • Master's degree in Electrical Engineering and 6+ years of experience in top level floorplanning (preferred).
  • Experience in scripting languages like Python, Tcl, or Perl and EDA tools (preferred).

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