ASIC Implementation Engineer PD

Broadcom

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $121,900–$195,000 / yr
Posted: 57 days ago
Freshness: Confirmed live 2 days ago
Closes: Jan 12, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k

This role $158k

$108k most similar roles pay here $252k

This role pays less than 84% of similar roles. Most pay $175,000–$227,350 — the shaded band above. At the midpoint, this role pays about $158k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer PD

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The ASIC Implementation Engineer PD joins the Asic Products Division to work on next generation Artificial Intelligence and PCIe Switch Products. This role involves managing the full physical design process from RTL to silicon tape-out, specifically focusing on top level floorplanning, partition creation, clock tree delivery, and power grid design. The engineer will resolve chip integration issues, manage cross-functional interactions regarding I/O and bump planning, and perform technical evaluations of vendors and IP. Key responsibilities include managing multi-voltage domain designs, structured clocks, and custom routes while resolving DRC, LVS, and EMIR issues for advanced nodes. Required skills include experience with technologies like Switch Fabric, SerDes, HBM, and chiplets. The candidate should be proficient in EDA tools and scripting languages such as Python, Tcl, or Perl to improve floorplan implementation methodologies.

Skills

Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools Switch Fabric DDR SerDes HBM Chiplet Power Grid Design Multi-voltage Domain

What you'll do

Own chip floor planning, partition creation, and the delivery of top level partitions.
Manage clock tree design and distribution across top level partitions.
Resolve physical design issues related to chip integration and assembly.
Coordinate cross-functional interactions regarding top level floorplanning, I/O, and bump planning with the package team.
Develop and improve floorplan implementation methodologies using industry and internal tools.
Perform technical evaluations of vendors and IP to meet specific design requirements.
Resolve chip level DRC, LVS, and EMIR issues for advanced nodes.

What we're looking for

Bachelor's degree in Electrical Engineering and 8+ years of experience in top level floorplanning.
Master's degree in Electrical Engineering and 6+ years of experience in top level floorplanning.
Expertise in physical design aspects from RTL to silicon tape-out.
Experience with advanced nodes resolving chip level DRC, LVS, and EMIR issues.
Experience with multi-voltage domain designs, power grid design, and structured clocks.
Experience with various technologies including Switch Fabric, High Speed DDR, SerDes, HBM, and chiplets.
Proficiency in scripting languages such as Python, Tcl, or Perl and EDA tools.
Ability to work in person at the San Jose site.

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