ASIC Implementation Engineer

Broadcom

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
81 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 19, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $187k
$133k most similar roles pay here $240k

This role pays less than 52% of similar roles. Most pay $168,500–$216,562 — the shaded band above. At the midpoint, this role pays about $187k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · ASIC Implementation Engineer

The ASIC Implementation Engineer joins the Asic Products Division to drive next generation Artificial Intelligence and PCIe Switch Products. This role focuses on the physical design aspects of taking RTL to silicon tape-out, specifically owning chip floor planning, partition creation, clock tree delivery, and top level partitions. The engineer will resolve issues related to chip integration and assembly while managing cross-functional interactions regarding I/O and bump planning with the package team. They will develop implementation methodologies using internal and industry tools while performing technical evaluations of vendors and IP. Required expertise includes die size estimation, partitioning, clocking, pin planning, and resolving DRC/LVS/EMIR issues for advanced nodes. Technical skills include experience with Switch Fabric, SerDes, HBM, and multi-voltage designs, alongside proficiency in Python, Tcl, or Perl scripting languages and various EDA tools.

What you'll do

  • Own chip floor planning, partition creation, and the delivery of top level partitions.
  • Manage clock tree design and delivery for top level partitions.
  • Resolve physical design issues related to chip integration and assembly.
  • Coordinate cross-functional interactions regarding top level floorplanning, I/O, and bump planning with the package team.
  • Develop and improve floorplan implementation methodologies using industry and internal tools.
  • Perform technical evaluations of vendors and IP to meet specific design requirements.
  • Resolve chip level DRC, LVS, and EMIR issues for advanced nodes.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 12+ years of experience in top level floorplanning.
  • Master's degree in Electrical Engineering with 10+ years of experience in top level floorplanning.
  • Expertise in die size estimation, partitioning, clocking, and pin planning.
  • Experience resolving chip level DRC/LVS/EMIR issues for advanced nodes.
  • Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
  • Experience with hierarchical floorplanning, power grid design, structured clocks, and top level pipeline planning.
  • Proficiency in scripting languages such as Python, Tcl, or Perl and various EDA tools.
  • Ability to work in person at the San Jose site.

More like this

Similar roles

ASIC Implementation Engineer PD

Broadcom

San Jose, CA 57 days ago $121,900$195,000
Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools Switch Fabric DDR SerDes HBM Chiplet Power Grid Design Multi-voltage Domain
8+ yrs exp

ASIC Implementation Engineer

Broadcom

San Jose, CA 137 days ago $120,000$192,000
Physical Design STA Floorplanning Layout Clock Tree Synthesis EM/IR Analysis TCL Perl EDA Tools RTL Tape-out
8+ yrs exp

Physical Design Engineer

Qualcomm

San Diego, CA +2 25 days ago $123,100$250,000
ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime
4+ yrs exp

GPU Physical Design Engineer

Apple Inc

Santa Clara, CA 144 days ago $184,700$324,800
Physical Design PPA Optimization RTL Synthesis DFT Floorplanning Place and Route TCL Perl Python ASIC Multi-voltage Design for Yield Thermal Management Tapeout
10+ yrs exp

ASIC Implementation Engineer STA

Broadcom

San Jose, CA 57 days ago $143,800$230,000
STA SDC Tcl Python Perl Shell ASIC MMMC Cadence Synopsys Signal Integrity IR-drop DFT PVT ATPG MBIST
10+ yrs exp

ASIC Engineer

Cisco

Remote (San Jose, CA) 15 days ago $155,000$222,600
DFT Python Perl Tcl Shell Scripting Verilog SystemVerilog LSF SDC EDA Tools ASIC Design Scan Insertion ATPG SPF Generation Pattern Simulation Regression Frameworks
5+ yrs exp Remote