ASIC Implementation Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
6 days ago
Closes
Dec 19, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $187k
$133k most similar roles pay here $240k

This role pays more than 50% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 97 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 95 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer

Broadcom seeks a senior-level ASIC top level floorplan Physical Design Engineer to join its Asic Products Division, focusing on cutting-edge AI and PCIe Switch Products. This role entails managing chip floor planning, partition creation, clock tree delivery, and resolving physical design issues related to integration and assembly. The engineer will develop methodologies for floorplanning using both industry-standard and internal tools, evaluate vendors and IP, and collaborate closely with cross-functional teams including package engineering. Ideal candidates possess extensive experience in die size estimation, partitioning, clocking, and pin planning across various technologies such as switch fabric, high-speed DDR, and HBM. Strong skills in scripting languages like Python and EDA tools are essential, along with a background in resolving advanced node DRC/LVS/EMIR issues and multi-voltage domain designs.

What you'll do

  • Own chip floor planning, partition creation, and clock tree delivery.
  • Resolve physical design issues related to chip integration and assembly.
  • Manage cross-functional interactions with the package team for top level floorplanning.
  • Develop and improve floorplan implementation methodologies using industry tools.
  • Perform technical evaluations of vendors and IP, providing recommendations.

What we're looking for

  • Bachelors in Electrical Engineering with 12+ years or Masters with 10+ years of top-level floorplanning experience.
  • Extensive experience in die size estimation, partitioning, clocking, and pin planning for advanced nodes.
  • Proven ability to resolve chip level DRC/LVS/EMIR issues and manage multi-voltage domain designs.
  • Experience with hierarchical floorplanning, power grid design, structured clocks, and custom routes.
  • Strong collaboration skills with design, package, and methodology teams during development phases.
  • Proficiency in scripting languages like Python, Tcl, or Perl and EDA tools for physical design tasks.

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