ASIC Implementation Engineer

Broadcom

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Quick summary

Work type: On-site
Location: San Jose, CA
Employment: Full-time
Posted: 127 days ago
Freshness: Confirmed live today
Closes: Dec 19, 2026
Nearby: 99+ roles within 25 mi

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Similar $193k

$141k $240k

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About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Implementation Engineer

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The ASIC Implementation Engineer joins the Asic Products Division to work on next generation Artificial Intelligence and PCIe Switch Products. This role involves taking RTL to silicon tape-out by owning chip floor planning, partition creation, clock tree delivery, and top level partitions. The engineer will resolve physical design issues related to chip integration and assembly while managing cross functional interactions for I/O and bump planning with the package team. Key responsibilities include developing floorplan implementation methodologies and performing technical evaluations of vendors and IP. Required skills include expertise in die size estimate, partitioning, clocking, and pin planning for technologies like Switch Fabric, SerDes, and HBM. Candidates must use scripting languages like Python, Tcl, or Perl along with various EDA tools to manage DRC, LVS, and EMIR issues.

Skills

Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools High Speed DDR SerDes HBM Chiplet Multi-voltage domain designs RDL implementation Power grid design

What you'll do

Own chip floor planning, partition creation, and the delivery of top-level partitions.
Manage clock tree synthesis and delivery for top-level partitions.
Resolve physical design issues related to chip integration and assembly.
Coordinate with the package team on top-level floorplanning, I/O, and bump planning.
Develop and improve floorplan implementation methodologies using industry and internal tools.
Perform technical evaluations of vendors and IP to meet design specifications.
Resolve chip-level DRC, LVS, and EMIR issues for advanced nodes.

What we're looking for

In-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
Experience in chip floor planning, partition creation, clock tree, and top level partition delivery.
Ability to resolve physical design issues related to chip integration and assembly.
Experience in developing and improving floorplan implementation methodologies using industry and internal tools.
Experience performing technical evaluations of vendors and IP to meet design specifications.
Bachelor's in Electrical Engineering and 12+ years of experience in top level floorplanning (preferred).
Master's degree in Electrical Engineering and 10+ years of experience in top level floorplanning (preferred).
Experience with scripting languages like Python, Tcl, or Perl and EDA tools (preferred).