ASIC FPGA Engineer

General Dynamics

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Remote

Quick summary

Work type
Remote
Location
Boise, IDSalt Lake City, UT
Salary
$103,585–$110,000 / yr
Posted
7 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $107k
$89k $237k
below market most similar roles pay here above market

This role pays less than 98% of similar roles. Most pay $163,846–$217,525 — the blue band above. At the midpoint, this role pays about $107k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1161 open roles on FindRole.

Listed pay typically runs $124,397–$153,102 across 1008 roles with salary data.

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At a glance

TL;DR · ASIC FPGA Engineer

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As an ASIC FPGA Engineer within the Idaho Scientific group, you will join a cross-functional team to design and deploy secure system solutions for mission-critical products. Your daily responsibilities include contributing to FPGA design, simulation, verification, and documentation. You will create test plans, define module interfaces, and support the development flow including synthesis, place and route, timing, and power utilization. The role requires proficiency in VHDL or Verilog hardware description languages, embedded C or C++ programming, and experience with Xilinx Vivado or Altera Quartus software. You must possess a strong understanding of computer architecture to solve technical problems. The work involves developing secure hardware solutions, potentially incorporating applied cryptography, cybersecurity principles for operational technology, secure boot processes, and RISC-V or other CPU microarchitectures.

Skills

FPGA ASIC VHDL Verilog C C++ Xilinx Vivado Altera Quartus RTL Computer Architecture RISC-V PCI Express DDR Cryptography Secure Boot Simulation Synthesis Place and Route

What you'll do

  • Create test and simulation plans that establish functional criteria for designs.
  • Define module interfaces and contribute to device design and simulation activities.
  • Contribute to system architecture, system simulation, and detailed design approaches.
  • Support the FPGA development flow including synthesis, place and route, timing, and power utilization.
  • Verify test results, analyze performance, and document designs and results.
  • Develop technical engineering products using established standards and tools throughout the ASIC/FPGA development life cycle.
  • Perform FPGA RTL development using VHDL or Verilog hardware description languages.
  • Develop test bench simulations to verify hardware functionality.

What we're looking for

  • U.S. citizenship is required.
  • Ability to obtain and maintain a Department of Defense Secret security clearance.
  • Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 2 years of relevant experience.
  • Master's degree plus 6 months of relevant experience.
  • Proven FPGA RTL development experience with a strong body of work in VHDL or Verilog.
  • Fluency in VHDL or Verilog hardware description languages and embedded C or C++ programming.
  • Experience with Xilinx Vivado and/or Altera Quartus software and developing test bench simulations.
  • Strong understanding of computer architecture and analytical problem-solving skills.
  • Active U.S. security clearance (preferred).
  • Working knowledge of applied cryptography (preferred).
  • Experience applying cybersecurity principles to operational technology and embedded systems (preferred).
  • Experience reverse engineering hardware and software (preferred).
  • Knowledge of the secure boot process (preferred).
  • Experience developing RISC-V or other CPU microarchitectures (preferred).
  • Experience with PCI Express or DDR controllers (preferred).

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