This role pays less than
92%
of similar roles. Most pay
$167,925–$217,625
— the shaded band above.
At the midpoint, this role pays about
$143k
versus about
$193k
for comparable roles.
Based on 240 similar postings.
Employer
About General Dynamics
General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.
General Dynamics currently has
1262 open roles
on FindRole.
Listed pay typically runs
$121,975–$150,000
across 1073 roles with salary data.
As an Advanced ASIC FPGA Design Engineer, you will join the engineering team to architect and implement high-performance FPGA designs targeting Xilinx and Microchip device families. Your daily responsibilities include performing synthesis, place-and-route, and timing closure using Vivado or Libero tools while employing advanced techniques like pipelining and floorplanning. You will develop block-level simulations in QuestaSim or ModelSim, create self-checking testbenches, and design high-speed interfaces for system integration. The role requires proficiency in VHDL, Verilog, or SystemVerilog, along with experience in AXI protocols and hardware implementations of cryptographic algorithms like AES or RSA. You will also contribute to CI/CD pipelines using GitLab and Python scripts while supporting lab bring-up activities. This position focuses on solving complex high-speed digital design challenges, including clock domain crossing and metastability mitigation for mission-critical systems.
Architect and implement high-performance FPGA designs using VHDL or Verilog for Xilinx and Microchip devices.
Perform synthesis, place-and-route, and timing closure using Vivado or Libero tools.
Execute block-level simulations with code coverage analysis using QuestaSim or ModelSim.
Create self-checking testbenches to verify design correctness automatically.
Design high-speed interfaces for inter-module communication and system integration.
Develop CI/CD pipelines for automated synthesis, simulation regression, and coverage tracking.
Perform on-target FPGA debug during lab bring-up using ILAs and JTAG-based tools.
What we're looking for
Bachelor's degree in Electrical or Computer Engineering (or related field) plus 5 years of experience, or a Master's degree plus 3 years of experience.
U.S. citizenship and the ability to obtain and maintain a Department of Defense Secret security clearance.
Proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design.
Experience with Xilinx Vivado or Microchip Libero tools for synthesis, implementation, and timing analysis on Xilinx and Microchip device families.
Ability to achieve timing closure at 300+ MHz clock rates and experience with high-speed digital design principles like pipelining and CDC.
Experience with FPGA simulation tools (QuestaSim or ModelSim) and writing self-checking testbenches.
Knowledge of AXI-Stream, AXI4, or similar on-chip bus protocols.
Experience with cryptographic algorithms, high-speed serial interfaces, CI/CD pipelines, scripting languages, and Xilinx IP cores (preferred).
FPGA
VHDL
Verilog
Digital Signal Processing
ModelSim
Synplicity
Xilinx Vivado
Altera Quartus
C
C++
C#
Matlab
Simulink
Git
Ethernet
SPI
UART
SDRAM
DDR3
JESD
PCIe