This role pays less than
70%
of similar roles. Most pay
$162,000–$216,250
— the shaded band above.
At the midpoint, this role pays about
$164k
versus about
$189k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
190 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,200
across 190 roles with salary data.
As an ASIC DFT Engineer II within the Silicon One team, you will focus on Design-for-Test requirements for hardware platforms powering switching, routing, and wireless products. You will collaborate with frontend RTL and backend physical design teams to implement features supporting ATE, in-system test, debug, and diagnostics. Your daily responsibilities include creating automation scripts to improve implementation efficiency, validating test timing and logic equivalency, and managing the integration of test logic across all phases of development. The role requires proficiency in SystemVerilog, Python, Tcl, or Perl for scripting. You will utilize specialized EDA tools including TestMax, Tetramax, Tessent, and PrimeTime for pattern generation and analysis. Technical expertise involves JTAG protocols, scan architectures, BIST, gate-level simulations using VCS, and understanding VLSI circuit behaviors like electromigration and timing concepts such as setup and hold times.
Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics.
Create and enhance automation scripts to improve implementation robustness and efficiency.
Drive DFT requirements early in the design cycle by collaborating with frontend RTL and backend Physical Design teams.
Validate test timing and logic equivalency of designs using SystemVerilog.
Utilize ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime for test pattern generation and analysis.
Integrate and validate test logic across all phases of implementation and post-silicon validation flows.
What we're looking for
Must have a Master's degree with 0 years of experience or a Bachelor's degree with 2 years of experience in ASIC Engineering or a related field.
Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST.
Familiarity or introductory hands-on exposure to EDA and ATPG tools.
Proficiency in scripting or coding using Python, Tcl, or Perl.
Experience working with gate-level simulations and debugging using simulators like VCS.
Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation (preferred).
Understanding of basic VLSI circuit physical behaviors and familiarity with basic timing concepts (preferred).
Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis (preferred).