This role pays less than
67%
of similar roles. Most pay
$152,875–$214,000
— the shaded band above.
At the midpoint, this role pays about
$164k
versus about
$183k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
190 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,200
across 190 roles with salary data.
As an ASIC Design Verification Eng II on the Silicon One team, you will play a critical role in developing data center solutions by verifying ASICs in simulation, emulation, and during bring-up to ensure seamless integration and performance of hardware platforms. You will be responsible for maintaining and enhancing existing verification environments, constructing test benches including scoreboards, agents, sequencers, and monitors, and writing test plans while debugging regression failures to achieve module verification closure. The role requires expertise in SystemVerilog and UVM methodology, along with scripting skills in Perl or Python. You will also manage functional coverage through code review and implementation. This position focuses on the technical challenge of verifying complex blocks, clusters, and top-level designs for SoCs within a high-performance hardware environment involving Veloce and HAPS tools.
Maintain and enhance existing design verification environments.
Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
Write comprehensive test plans and develop specific test cases.
Debug regression failures and drive projects toward module verification closure.
Ensure complete verification coverage through the implementation and review of code and functional coverage.
Verify ASICs in simulation, emulation, and during hardware bring-up to ensure optimal performance.
What we're looking for
Candidates must have a Master's degree with 0 years experience or a Bachelor's degree with 2 years experience in ASIC Engineering, Verification, or a related field.
Experience with SystemVerilog and UVM methodology is required.
Experience with scripting using Perl and/or Python is required.
Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks or clusters is preferred.
Experience with functional coverage and constrained random DV environments is preferred.
Experience in verifying complex blocks, clusters, and top level for SoC is preferred.
Experience with Veloce/HAPS is preferred.
Experience building test benches from scratch including SystemVerilog constraints, structures, and classes is preferred.