ASIC Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Irvine, CASan Jose, CA
Salary
$101,000–$162,000 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday
Closes
Jan 24, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $132k
$86k most similar roles pay here $238k

This role pays less than 94% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $132k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · ASIC Verification Engineer

As an ASIC Verification Engineer within the High Speed Interconnect Product group, you will contribute to the development of high-performance physical layer transceivers for AI data centers and enterprise networks. You will work across the full product development cycle, collaborating with marketing, architecture, firmware, and layout teams to verify communication ASICs. Your daily responsibilities include developing advanced verification environments and testbench components using SystemVerilog UVM, performing block and chip level verification, and creating scripts for infrastructure improvements. To succeed in this role, you must possess proficiency in HDL languages like Verilog, SystemVerilog, or VHDL. Additional strengths include experience with C/C++ and object-oriented programming, along with scripting skills in Python, PERL, or TCL. You will apply your knowledge of IEEE Ethernet protocols to solve complex chip architecture and design specification challenges.

What you'll do

  • Develop a thorough understanding of IEEE Ethernet protocols.
  • Analyze chip architecture, microarchitecture, and design specifications.
  • Develop advanced verification environments and testbench components using SystemVerilog UVM.
  • Perform block-level and chip-level verification tasks.
  • Create scripts and tools to improve infrastructure efficiency and quality.
  • Execute the full product development cycle from definition to production.

What we're looking for

  • A Bachelor's degree in Engineering with 5+ years of experience, or a Master's/PhD in Engineering for recent graduates.
  • Experience in ASIC design and verification or equivalent experience.
  • Proficiency in HDL languages such as Verilog, SystemVerilog, or VHDL.
  • Knowledge of logic design and electronic circuit design coursework.
  • Familiarity with C/C++ programming and Object Oriented Programming is a plus.
  • Proficiency in scripting languages such as Python, PERL, or TCL is a plus.
  • Understanding of IEEE Ethernet protocols and chip microarchitecture.
  • Ability to develop verification environments and testbench components in SystemVerilog UVM.

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