ASIC Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Irvine, CASan Jose, CA
Salary: $101,000–$162,000 / yr
Employment: Full-time
Posted: 62 days ago
Freshness: Confirmed live yesterday
Closes: Jan 24, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $132k

$86k $240k

below market most similar roles pay here above market

This role pays less than 95% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $132k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · ASIC Verification Engineer

Role Posting Log in to save

The ASIC Verification Engineer joins the High Speed Interconnect Product Group to support the development of high performance physical layer transceivers for AI data centers and enterprise networks. This role involves working across the full product development cycle from definition to production, collaborating with marketing, architecture, firmware, and layout teams. Key responsibilities include developing advanced verification environments and testbench components, performing block level and chip level verification, and creating infrastructure scripts for quality improvements. Candidates must possess a deep understanding of IEEE Ethernet protocols and chip microarchitecture. Required technical skills include proficiency in HDL languages like Verilog, SystemVerilog, or VHDL. Preferred competencies include C/C++ with Object Oriented Programming, along with scripting experience in Python, PERL, or TCL to enhance verification efficiency.

Skills

SystemVerilog UVM Verilog VHDL C++ C Python Perl TCL ASIC Design Logic Design Electronic Circuit Design IEEE Ethernet Object Oriented Programming Scripting Verification Environment

What you'll do

Develop a thorough understanding of IEEE Ethernet protocols.
Analyze chip architecture, microarchitecture, and design specifications.
Develop advanced verification environments and testbench components using SystemVerilog UVM.
Execute block-level and chip-level verification tasks.
Develop scripts and tools to improve infrastructure efficiency and quality.
Support the full product development cycle from definition to production.

What we're looking for

Must have a Master's or PhD degree in Engineering or a Bachelor's in Engineering with at least 3 years of related experience.
Must have a Bachelor's in Engineering and 5+ years of related experience.
Must have design/verification experience or equivalent experience.
Must have completed coursework in logic design and electronic circuit design.
Must be proficient in HDL languages such as Verilog, SystemVerilog, or VHDL.
Proficiency with C/C++ programming and hands-on exposure to Object Oriented Programming (preferred).
Proficiency with scripting in languages such as Python, PERL, or TCL (preferred).
Must be a self-motivated communicator, quick learner, and team player with a positive attitude.

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