ASIC Verification Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Irvine, CA
Employment: Full-time
Posted: 60 days ago
Freshness: Confirmed live today
Closes: Feb 20, 2027
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $189k

$134k $235k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $162,000–$216,250.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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The ASIC Verification Engineer joins the High Speed Interconnect Product Group to support the development of low-power, high-performance PHYs for cloud computing and server virtualization. This role involves the full product development lifecycle, where the engineer works with architecture, design, and firmware teams to bring complex designs from concept to production. Key responsibilities include developing a deep understanding of IEEE Ethernet protocols, designing and maintaining advanced verification environments and testbench components, and owning the verification process at both the block and chip levels. The candidate must demonstrate proficiency in HDL languages like SystemVerilog, Verilog, or VHDL, along with C/C++ and Object-Oriented Programming. Additional required skills include scripting in Python, Perl, or TCL to automate workflows and improve overall design quality.

Skills

SystemVerilog UVM Verilog VHDL C++ C Python Perl TCL ASIC Verification Logic Design Computer Architecture Networking Protocols IEEE Ethernet Object-Oriented Programming Scripting

What you'll do

Design and maintain advanced verification environments and testbench components using SystemVerilog UVM.
Own the verification process at both the block and chip levels to ensure first-pass silicon success.
Develop a deep understanding of the latest IEEE Ethernet protocols.
Develop custom scripts and tools to improve verification efficiency and design quality.
Work alongside architecture, design, and firmware teams to bring complex designs from concept to production.
Automate complex workflows using scripting languages like Python, Perl, or TCL.

What we're looking for

Master of Science in Electrical Engineering/Computer Science (New Grad) or Bachelor of Science in Electrical Engineering/Computer Science with 3+ years of experience.
3+ years of direct ASIC Design/Verification experience (required for BSEE/CS degree holders).
Strong grasp of logic design, computer architecture, and networking protocols.
Proficiency in HDL languages such as SystemVerilog, Verilog, or VHDL.
Strong C/C++ skills and a solid understanding of Object-Oriented Programming (preferred).
Experience with scripting in Python, Perl, or TCL to automate complex workflows (preferred).
Ability to communicate complex technical concepts effectively.

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