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Active Keyword: ASIC Design STA Engineer Remove filter Clear all

6 of up to 20 (filtered)

Senior Staff ASIC Design Engineer

Amd

San Jose, CA 7 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes
Hybrid
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ASIC Design Engineer, STA

Cisco

Remote (San Jose, CA) 36 days ago $155,000–$222,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
STA Verilog SystemVerilog ASIC Design Physical Design Spice ECO Timing Analysis Extraction PnR
5+ yrs exp Remote
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Manager, ASIC Design Engineering

SpaceX

Hawthorne, CA 134 days ago $190,000–$245,000
Actively hiring Confirmed live yesterday Trusted Above market
ASIC FPGA Verilog System Verilog RTL Synthesis Timing Closure AXI AHB Python TCL VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II
5+ yrs exp
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ASIC Design STA Engineer

Amd

San Jose, CA 147 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
STA SDC TCL Synopsys Design Compiler PrimeTime RTL Synthesis P&R EDA Tools Spyglass Fishtail Linux QoR Scripting ASIC Design
Hybrid
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Principal ASIC Design Engineer

SpaceX

Hawthorne, CA 162 days ago $200,000–$285,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure
8+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Hawthorne, CA 163 days ago $160,000–$225,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure Formality
5+ yrs exp
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