ASIC Design Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$100,000–$166,750 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $133k
$86k most similar roles pay here $233k

This role pays less than 85% of similar roles. Most pay $152,875–$216,562 — the shaded band above. At the midpoint, this role pays about $133k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Design Engineer

Role Posting Log in to save

As an ASIC Design Engineer - New College Grad 2027 on the GPU Design team, you will implement, document, and deliver high performance, area, and power efficient RTL to meet specific design targets. Your daily responsibilities include analyzing architectural trade-offs based on features and system limitations, crafting micro-architecture, and delivering fully verified, synthesis and timing clean designs. You will collaborate with architects, verification teams, and back-end teams while working on various IPs such as work schedulers, time distribution systems, interrupt controllers, and DMA engines. The role requires expertise in Verilog, RTL development, logic synthesis, and timing analysis. Candidates should possess knowledge of computer architecture, digital systems, and VLSI design. Preferred skills include C/C++, Python, or Perl, along with experience in arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches to support GPU and SoC development.

What does a ASIC Design Engineer earn in California?

Median $214000 from 45 postings across 7 companies.

See salary data

Skills

RTL Verilog ASIC Design VLSI Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl Computer Architecture DMA Bus Protocols Cache Digital Systems

What you'll do

  • Implement and document high-performance, area-efficient RTL to meet specific design targets and requirements.
  • Analyze architectural trade-offs based on features, performance needs, and system limitations.
  • Craft micro-architecture and deliver fully verified, synthesis/timing clean designs.
  • Develop a wide range of IPs including work schedulers, interrupt controllers, and DMA engines.
  • Architect features to facilitate silicon debugging and support post-silicon validation activities.
  • Coordinate with cross-functional teams across verification, synthesis, timing, and back-end departments.

What we're looking for

  • Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Knowledge of micro-architecture and RTL development using Verilog.
  • Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Required exposure to Digital systems, VLSI design, Computer Architecture, and Computer Arithmetic.
  • Strong interpersonal skills and ability to work as an excellent teammate.
  • Proficiency in C/C++, Python, or Perl (preferred).
  • Good debugging and analytical skills (preferred).
  • Experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches (preferred).

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