ASIC Design and Integration Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 95% of similar roles. Most pay $162,000–$216,562 — the shaded band above. At the midpoint, this role pays about $255k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · ASIC Design and Integration Engineer

Role Posting Log in to save

The ASIC Design and Integration Engineer joins the Silicon Engineering team to develop custom SoCs that drive product performance and efficiency. This role involves the design, implementation, and verification of complex ASICs while collaborating with cross-functional hardware and software teams to integrate digital designs into sophisticated systems. Daily responsibilities include developing RTL using SystemVerilog, performing synthesis, conducting timing analysis, and executing power optimization to meet specific PPA goals. The candidate will also create detailed micro-architecture documentation and engage with simulation-based and formal verification teams. Required technical skills include proficiency in SystemVerilog, RTL design, and front-end chip development processes such as CDC, RDC, LINT, and LEC. Additional expertise includes high-speed I/O design, PCIe protocols, low-power design techniques, and experience with FPGA prototyping to solve complex hardware integration challenges.

Skills

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification Simulation

What you'll do

Design and implement complex ASICs using SystemVerilog for RTL development.
Perform synthesis and conduct timing analysis to meet PPA goals.
Execute power optimization strategies to improve chip efficiency.
Validate designs through collaboration with simulation-based and formal verification teams.
Integrate digital designs into complex SoCs in coordination with hardware and software teams.
Create detailed micro-architecture and design documentation.
Manage front-end chip development processes including CDC, RDC, LINT, and LEC.
Design high-speed I/O components and implement relevant protocols like PCIe.

What we're looking for

Bachelor of Science degree required.
Minimum of 10 years of relevant industry experience.
At least 8 years of proven experience in ASIC design, including RTL design and verification.
Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Experience with high-speed I/O design and protocols like PCIe.
Hands-on experience in front-end chip development processes such as CDC, RDC, LINT, and LEC.
Knowledge of low-power design techniques and power optimization strategies.
Familiarity with custom ASIC design and FPGA prototyping.

Similar roles

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 32 days ago $129,300–$194,700

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design

Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification

10+ yrs exp

Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification High-speed I/O PCIe FPGA Prototyping CDC RDC LINT LEC Low-power Design

3+ yrs exp

Save

ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 32 days ago

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization CDC RDC Formal Verification Simulation Micro-architecture

Save

ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 22 days ago $184,700–$324,800

RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security

10+ yrs exp

Save

ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 38 days ago $150,400–$277,600

RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist

3+ yrs exp

Save