ASIC Design and Integration Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $189k

$141k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $162,000–$216,562.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design and Integration Engineer

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The ASIC Design and Integration Engineer joins the Silicon Engineering team to develop custom SoCs that drive performance and efficiency for various products. In this role, you will perform the design, implementation, and verification of complex ASICs while creating detailed micro-architecture and design documentation. Daily responsibilities include developing RTL using SystemVerilog, performing synthesis, conducting timing analysis, and executing power optimization to meet specific PPA goals. You will collaborate with cross-functional hardware and software teams to integrate digital designs into complex SoCs. The role requires expertise in SystemVerilog, RTL design, and front-end chip development processes such as CDC, RDC, LINT, and LEC. Additional technical requirements include experience with high-speed I/O design, PCIe protocols, low-power design techniques, and FPGA prototyping to solve critical hardware integration challenges within the silicon engineering domain.

Skills

SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification

What you'll do

Design and implement complex ASICs using SystemVerilog for RTL development.
Perform synthesis and front-end chip development processes including CDC, RDC, LINT, and LEC.
Execute simulation-based and formal verification to ensure robust design validation.
Integrate digital designs into complex SoCs in coordination with hardware and software teams.
Conduct timing analysis and implement power optimization strategies to meet PPA goals.
Design high-speed I/O components and implement relevant protocols like PCIe.
Create detailed micro-architecture and technical design documentation.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
At least 8 years of proven experience in ASIC design, including RTL design and verification.
Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Experience with high-speed I/O design and protocols like PCIe.
Hands-on experience in front-end chip development processes such as CDC, RDC, LINT, and LEC.
Knowledge of low-power design techniques and power optimization strategies.
Familiarity with custom ASIC design and FPGA prototyping.
Strong analytical problem-solving skills and ability to work effectively in cross-functional teams.

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