ASIC Chip Lead

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CAIrvine, CA
Employment
Full-time
Posted
12 days ago
Freshness
Confirmed live today
Closes
Mar 15, 2027
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $208k
$146k most similar roles pay here $259k

This listing doesn't post a salary. Most similar roles pay $175,800–$240,150.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 224 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 156 roles with salary data.

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At a glance

TL;DR · ASIC Chip Lead

Role Posting Log in to save

As an ASIC Chip Lead, you will lead and implement chips in high-volume consumer devices and satellite projects using ultra-low power 40nm, 16nm, and 7nm nodes. Your daily responsibilities include physical implementation of blocks and top-level designs, floorplanning with multi-power domains, PG planning, block-shaping, and clock-tree implementation. You will perform physical verification at both the block and chip levels while conducting static and dynamic IR drop analysis alongside signal and power EM checks. Collaborating with internal design, IP, and library teams, you will develop methodologies for physical design and timing closure. The role requires expertise in Cadence Innovus, Calibre, Formality, LEC, and VCLP tools. You must possess TCL scripting skills, with Python as a plus, to support the technical requirements of complex chip integration and power-intent specifications.

Skills

Cadence Innovus TCL Python Physical Design STA Timing Closure Calibre Formality LEC VCLP IR Drop Analysis EM Check Floorplanning RTL ESD Analog Integration

What you'll do

  • Implement chips in high-volume consumer devices across various advanced technology nodes.
  • Execute physical implementation of blocks and top-level designs.
  • Perform floorplanning including multi-power domains, PG planning, and clock-tree implementation.
  • Conduct physical verification for both block and chip levels.
  • Perform static and dynamic IR drop analysis along with signal and power EM checks.
  • Develop methodologies and flows for Physical Design and Timing Closure.
  • Coordinate with internal and external teams to meet design, IP, and library requirements.
  • Utilize TCL scripting and Cadence Innovus tools to complete tapeouts.

What we're looking for

  • BS in Electrical Engineering plus 12 years of experience or MS in Electrical Engineering plus 10 years of experience.
  • Experience with multiple tapeouts and extensive hands-on knowledge of tools like Innovus, VCLP, Formality, LEC, timing closure, and Calibre.
  • Proficiency in Cadence Innovus is essential.
  • TCL scripting is required.
  • Knowledge of ESD, IO padring, Analog integration, and various package types is preferred.
  • Python skills are preferred.
  • Knowledge of AI tools is preferred.

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