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Active Keyword: ASIC Chip Lead Remove filter Clear all

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ASIC Chip Lead

Broadcom

San Jose, CA +1 12 days ago
Actively hiring Confirmed live today High trust
Cadence Innovus TCL Python Physical Design STA Timing Closure Calibre Formality LEC VCLP IR Drop Analysis EM Check Floorplanning RTL ESD Analog Integration
10+ yrs exp
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Senior Chip Lead Engineer SoC/ASIC

Amd

San Jose, CA 32 days ago $164,000–$246,000
Actively hiring Confirmed live today High trust Competitive pay
ASIC FPGA Verilog SystemVerilog VHDL RTL Design Physical Design Timing Closure Power Optimization DFT Silicon Validation EDA Tools Device Drivers Low-level Software AI/ML Accelerators
10+ yrs exp
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Chip Lead, ASIC Director

Amd

San Jose, CA 130 days ago $248,800–$373,200
Actively hiring Confirmed live today High trust Above market
ASIC RTL Physical Design Timing Closure Post-silicon Validation FPGA Tapeout Verification Custom Design Design for Test Floorplan Architecture
Hybrid
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